公开(公告)号：US07512856B2

公开(公告)日：2009-03-31

申请号：US11562424

申请日：2006-11-22

Applicant: Tzu-Pin Shen ,  Shang-Chih Hsieh

Inventor： Tzu-Pin Shen ,  Shang-Chih Hsieh

IPC: G01R31/28

CPC classification number: G01R31/318541

Abstract: The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outputting the non-test data or the test data as the input data; a control circuit, coupled to a driving clock, for controlling the latch circuit to latch the input data as the output data according to the driving clock; and a scanning circuit, coupled to the driving clock and the latch circuit, for scanning the output data of the latch circuit to generate a scanning data according to the driving clock.

Abstract translation: 本发明公开了一种寄存器电路。 寄存器电路包括用于锁存输入数据以产生输出数据的锁存电路; 输入信号选择电路，分别耦合到非测试数据和测试数据，用于选择性地输出非测试数据或测试数据作为输入数据; 耦合到驱动时钟的控制电路，用于根据驱动时钟控制锁存电路锁存输入数据作为输出数据; 以及耦合到驱动时钟和锁存电路的扫描电路，用于扫描锁存电路的输出数据，以根据驱动时钟生成扫描数据。

公开(公告)号：US07493600B2

公开(公告)日：2009-02-17

申请号：US10904215

申请日：2004-10-29

Applicant: Cheng-Yen Huang

Inventor： Cheng-Yen Huang

IPC: G06F9/44 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3806

Abstract: A method for verifying a branch prediction mechanism and an accessible recording medium for storing a verification program are provided. The method is used for verifying the branch prediction mechanism, such as a branch target buffer (BTB), in a processor. The method comprises providing and executing a verification program in the processor. The verification program comprises at least one branch instruction, which determines whether to use a recursive call and execute the verification program according to a given condition.

Abstract translation: 提供了一种用于验证分支预测机制的方法和用于存储验证程序的可访问记录介质。 该方法用于在处理器中验证诸如分支目标缓冲器（BTB）之类的分支预测机制。 该方法包括在处理器中提供并执行验证程序。 验证程序包括至少一个分支指令，该指令决定是否使用递归调用，并根据给定条件执行验证程序。

公开(公告)号：US07465970B2

公开(公告)日：2008-12-16

申请号：US11382700

申请日：2006-05-10

Applicant: Jeng-Huang Wu ,  Chiung-Yu Feng ,  Chien-Chih Huang ,  Yu-Wen Tsai

Inventor： Jeng-Huang Wu ,  Chiung-Yu Feng ,  Chien-Chih Huang ,  Yu-Wen Tsai

IPC: H01L27/02 ,  H01L27/10

CPC classification number: H01L27/0207

Abstract: A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Abstract translation: 半导体布局包括p基板，在p基板上形成的第一半导体单元，以及形成在与p基板相邻的第一半导体单元上的第二半导体单元。 第一半导体单元和第二半导体单元的总高度是标准半导体单元的高度的两倍，并且根据第一半导体单元的高度来调整第二半导体单元的高度。

公开(公告)号：US20080297131A1

公开(公告)日：2008-12-04

申请号：US11756859

申请日：2007-06-01

Applicant: Yan-Hua Peng ,  Uei-Shan Uang ,  Mei-Show Chen

Inventor： Yan-Hua Peng ,  Uei-Shan Uang ,  Mei-Show Chen

IPC: G05F3/20

CPC classification number: G05F3/30

Abstract: A bandgap reference circuit includes a reference current generator for respectively generating a first reference current on a first current path and a second reference current on a second current path, a current mirror for generating a third reference current on a third current path based on the first and second reference currents, an operation amplifier for rendering the first reference current substantially identical to the second reference current and a feedback circuit for rendering a node voltage on the first current path substantially identical to another node voltage on the third current path, so as to eliminate possible errors caused by a channel length modulation effect in the current mirror.

Abstract translation: 带隙参考电路包括：参考电流发生器，用于分别在第一电流路径上产生第一参考电流，在第二电流路径上产生第二参考电流;电流镜，用于基于第一电流路径产生第三电流路径上的第三参考电流 和第二参考电流，用于使第一参考电流基本上与第二参考电流相同的运算放大器和用于使第一电流路径上的节点电压基本上与第三电流路径上的另一节点电压相同的反馈电路，以便 消除由电流镜中的通道长度调制效应引起的误差。

公开(公告)号：US07394241B2

公开(公告)日：2008-07-01

申请号：US11380217

申请日：2006-04-26

Applicant: Yu-Wen Tsai

Inventor： Yu-Wen Tsai

IPC: G01R31/28

CPC classification number: G01R31/2617

Abstract: A method for testing power switches using a logic gate tree, the method includes providing a logic gate tree electrically connected to a plurality of power switches, each output node of the plurality of power switches being electrically connected to a corresponding input node of a logic gate of the logic gate tree; applying a pattern of control signals to the plurality of power switches for controlling on-off states of the plurality of power switches; and determining whether an output voltage signal of an output node of the logic gate tree matches a predetermined value corresponding to the pattern of control signals.

Abstract translation: 一种使用逻辑门树测试功率开关的方法，所述方法包括提供电连接到多个功率开关的逻辑门树，所述多个功率开关中的每个输出节点电连接到逻辑门的对应输入节点 的逻辑门树; 对所述多个电源开关施加控制信号的模式，以控制所述多个电力开关的开 - 关状态; 以及确定逻辑门树的输出节点的输出电压信号是否与对应于控制信号的模式的预定值相匹配。

公开(公告)号：US20080111823A1

公开(公告)日：2008-05-15

申请号：US11558948

申请日：2006-11-13

Applicant: Yang-Je Fan ,  Chun-Hung Lin ,  Tzu-Lan Shen

Inventor： Yang-Je Fan ,  Chun-Hung Lin ,  Tzu-Lan Shen

IPC: G09G5/39

CPC classification number: G06T3/4092 ,  G06T1/60

Abstract: A graphics processing system for processing an input image to an output image. A memory buffer includes a number of line buffers for storing the input image. A sampling controller samples sampling points of the input image, scales the input image by a sampling polynomial equation, and generates a scaled image. A window filter filters the scaled image by a filter polynomial equation to generate the output image. A memory controller determines the number of the line buffers according to the sampling polynomial equation and the filter polynomial equation.

Abstract translation: 一种用于将输入图像处理到输出图像的图形处理系统。 存储器缓冲器包括用于存储输入图像的多个行缓冲器。 采样控制器对输入图像的采样点进行采样，通过采样多项式方程对输入图像进行缩放，并生成缩放图像。 窗口滤波器通过滤波多项式方程滤波缩放后的图像，以生成输出图像。 存储器控制器根据采样多项式方程和滤波器多项式方程确定行缓冲器的数量。

公开(公告)号：US07366917B2

公开(公告)日：2008-04-29

申请号：US10711413

申请日：2004-09-17

Applicant: Yung-Cheng Shih

Inventor： Yung-Cheng Shih

IPC: G06F11/30 ,  G06F7/04 ,  H04L9/00 ,  H04L9/32

CPC classification number: G06F21/602 ,  G06F21/79

Abstract: A method for accessing discrete data includes transmitting a write command to a memory, determining whether each data following a header of the file needs to be encrypted according to a data format of a file that is to be written into the memory, transmitting the file header and each data following the file header to a logic unit, turning on the logic unit for encrypting the data determined to be encrypted and writing the encrypted data into the memory, turning off the logic unit for writing the data determined not to be encrypted into the memory directly, and sending a first response signal from the memory when the writing of the file is finished.

Abstract translation: 用于访问离散数据的方法包括向存储器发送写命令，确定是否需要根据要写入存储器的文件的数据格式来加密文件头部后面的每个数据，发送文件头 并将文件头后面的每个数据连接到逻辑单元，打开用于加密被确定为加密的数据的逻辑单元，并将加密数据写入存储器，关闭逻辑单元，将确定为不加密的数据写入到 直接写存储器，并且当写入文件完成时从存储器发送第一响应信号。

公开(公告)号：US07339398B2

公开(公告)日：2008-03-04

申请号：US11162531

申请日：2005-09-14

Applicant: Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

Inventor： Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

IPC: H03K19/003

CPC classification number: H03K19/0005

Abstract: A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up array control unit and a pull-down array control unit. The pull-up array control unit controls the pull-up impedance of the driver by detecting a voltage from a first voltage divide point between the first reference impedance and the dummy pull-up array. The pull-down array control unit controls the pull-down impedance of the driver by detecting a voltage from a second voltage divide point between the second reference impedance and the dummy pull-down array.

Abstract translation: 提供了用于确定至少一个驱动器的阻抗的驱动器阻抗控制装置和系统。 驱动器阻抗控制装置包括第一参考阻抗，第二参考阻抗，虚拟上拉阵列，虚拟下拉阵列，上拉阵列控制单元和下拉阵列控制单元。 上拉阵列控制单元通过检测来自第一参考阻抗和虚拟上拉阵列之间的第一分压点的电压来控制驱动器的上拉阻抗。 下拉阵列控制单元通过检测来自第二参考阻抗和虚拟下拉阵列之间的第二分压点的电压来控制驱动器的下拉阻抗。

公开(公告)号：US07327551B2

公开(公告)日：2008-02-05

申请号：US11561416

申请日：2006-11-19

Applicant: Chih-Fu Chien ,  Chao-Chi Lee ,  Cheng-Chung Chou

Inventor： Chih-Fu Chien ,  Chao-Chi Lee ,  Cheng-Chung Chou

IPC: H01G4/00

CPC classification number: H01L28/60 ,  H01L23/50 ,  H01L23/5223 ,  H01L27/1085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set includes a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.

Abstract translation: 提供电容器结构。 电容器结构配置在基板中。 电容器结构包括多个电极组，至少第一导电插头和至少第二导电插头。 电极组彼此对应并且设置在衬底的不同层中。 每个电极组包括第一电极和围绕前者的第二电极。 此外，第一导电插塞和第二导电插头设置在两个相邻的电极组之间。 两个相邻电极组的第一电极彼此对应并且通过第一导电插塞彼此电连接。 类似地，两个相邻电极组的第二电极彼此对应并且通过第二导电插塞彼此电连接。

公开(公告)号：US20080022245A1

公开(公告)日：2008-01-24

申请号：US11560838

申请日：2006-11-17

Applicant: Yu-Wen Tsai ,  Jeng-Huang Wu

Inventor： Yu-Wen Tsai ,  Jeng-Huang Wu

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The forth device region is arranged between the third device region and the forth conductor on the substrate.

Abstract translation: 提供了在标准单元集成电路中使用的具有高性能和高密度设计的布局架构。 布局架构包括衬底，第一导体，第二导​​体，第三导体，第四导体，第一器件区域，第二器件区域，第三器件区域和第四器件区域。 第一器件区域布置成与衬底上的第一导体相邻。 第二器件区域布置成与衬底上的第一器件区域相邻并且布置在第二导体的下方。 第三器件区域布置成与衬底上的第二器件区域相邻并且布置在第三导体的下方。 第四器件区域布置在衬底上的第三器件区域和第四导体之间。