公开(公告)号：US08090062B2

公开(公告)日：2012-01-03

申请号：US12211324

申请日：2008-09-16

Applicant: Dharani Naga Sailaja Sankabathula ,  Partha Sarathy Murali ,  Logeshwaran Vijayan ,  Nagaraja Reddy Anakala

Inventor： Dharani Naga Sailaja Sankabathula ,  Partha Sarathy Murali ,  Logeshwaran Vijayan ,  Nagaraja Reddy Anakala

IPC: H04L27/08

CPC classification number: H03G3/3052 ,  H04L27/0006 ,  H04L27/2647

Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.

Abstract translation: 分组检测控制器接受来自AGC控制器的输入，其指示增加的信号能量的存在以及AGC处理的完成，并且产生用于暂停AGC过程的输出。 分组检测控制器还接收多个IQ接收机流并且形成单个流以供分组检测器使用，该分组检测器可以由指示信噪比是高于还是低于特定阈值的SNR_MODE控制，以及表示PD_RESET信号的PD_RESET信号 不会发生数据包检测。 控制器还接收一个指示分组检测完成的PACKET_DET信号。 如果产生分组检测，分组检测控制器检查输入的接收机流并暂停AGC处理，或者如果需要AGC过程则暂停分组检测器。

公开(公告)号：US08081700B2

公开(公告)日：2011-12-20

申请号：US12134215

申请日：2008-06-06

Applicant: Karthik Vaidyanathan ,  Sailaja Dharani Naga Sankabathula

Inventor： Karthik Vaidyanathan ,  Sailaja Dharani Naga Sankabathula

IPC: H04B7/02 ,  H04L1/02

CPC classification number: H04B7/0443

Abstract: A transmit power allocation method for computing a transmit beamforming W matrix for a N streams of data, the method has a first step of measuring a receive channel characteristic H matrix, a second step of decomposing the H matrix into a U matrix which is formed from the left eigenvectors of the H matrix, an Σ matrix which is a diagonal matrix formed from the square roots of the eigenvalues of said H matrix and re-ordered by strength, and a VT matrix with rows comprising the right eigenvectors of H, such that UΣVT=H. The transmit beamforming W matrix is then formed from the re-ordered V matrix of the previous decomposition. Optional waterfilling methods for a plurality of subcarriers may then be done using either a minimum mean square error, an optimal signal to noise ratio, or any other waterfilling method which optimizes a desired metric, such as signal to noise ratio or minimum mean square error.

Abstract translation: 一种用于计算N个数据流的发送波束形成W矩阵的发送功率分配方法，所述方法具有测量接收信道特性H矩阵的第一步骤，将所述H矩阵分解成U矩阵的第二步骤，所述U矩阵由 H矩阵的左特征向量，＆Sgr; 矩阵，其是由所述H矩阵的特征值的平方根和由强度重新排序的对角矩阵，以及具有包括H的右特征向量的行的VT矩阵，使得U＆Sgr; VT = H。 然后从先前分解的重排V矩阵形成发射波束形成W矩阵。 然后可以使用最小均方误差，最佳信噪比或者优化所需度量（例如信噪比或最小均方误差）的任何其它灌水方法来完成多个子载波的可选填埋方法。

公开(公告)号：US08077591B2

公开(公告)日：2011-12-13

申请号：US12146444

申请日：2008-06-26

Applicant: Partha Sarathy Murali ,  Paul Reuben Vincent ,  Karthik Vaidyanathan ,  Phanimithra Gangalakurti

Inventor： Partha Sarathy Murali ,  Paul Reuben Vincent ,  Karthik Vaidyanathan ,  Phanimithra Gangalakurti

IPC: H04B7/185 ,  H04B17/02 ,  H04J11/00

CPC classification number: H04L27/2675 ,  H04L27/261 ,  H04L27/2659

Abstract: A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs.

Abstract translation: 用于识别与多个接收的OFDMA子载波相关联的最大载波与噪声干扰比（CINR）的无线信号处理器具有候选发生器，用于通过基于接收到的子载波的特定集合形成候选值，形成候选值 所接收的子载波与可能的整数前导码偏移和可能的前导码值组合。 候选评估器选择哪个可能的前导码值和整数频率偏移值具有最大CINR，并且将具有IFO和前导索引的最大CINR提供为输出。

公开(公告)号：US07761688B1

公开(公告)日：2010-07-20

申请号：US11899557

申请日：2007-09-06

Applicant: Heonchul Park

Inventor： Heonchul Park

IPC: G06F9/00

CPC classification number: G06F9/3867 ,  G06F9/3851

Abstract: An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage. The various stages are provided a thread ID such that alternating stages use a first thread ID, and the other stages use a second thread ID. Each stage which requires access to thread ID specific context information uses the thread ID to specify this context information.

Abstract translation: 按顺序发行的顺序完成微控制器包括流水线核心，其连续地包括获取地址级，程序访问级，解码级，第一执行级，第二执行级，存储器访问级和 回写阶段 提供各个阶段的线程ID，使得交替阶段使用第一线程ID，并且其他阶段使用第二线程ID。 需要访问线程ID特定上下文信息的每个阶段使用线程ID来指定该上下文信息。

公开(公告)号：US07298799B1

公开(公告)日：2007-11-20

申请号：US10795817

申请日：2004-03-08

Applicant: Narasimhan Venkatesh ,  Sankabathula Dharani Naga Sailaja ,  Murali Partha Sarathy

Inventor： Narasimhan Venkatesh ,  Sankabathula Dharani Naga Sailaja ,  Murali Partha Sarathy

IPC: H04L27/06

CPC classification number: H04B1/7093 ,  H04B1/7077 ,  H04B1/712

Abstract: A decision processor for 802.11b codewords for 1 Mb and 2 Mb data rates includes a sliding correlator for the acquisition of correlation peaks. During a training interval, these correlation peaks are summed into a channel profile memory. The correlation peaks corresponding to a codeword are added into the channel profile memory, and correlation peaks corresponding to the inverse of this codeword are inverted and added into the channel profile memory during the training interval. After the training interval, a decision interval follows whereby correlation peaks are multiplied by the complex conjugate of the contents of the channel profile memory. The multiplication results are accumulated over a codeword window interval to produce a decision output.

Abstract translation: 用于1Mb和2Mb数据速率的用于802.11b码字的决策处理器包括用于获取相关峰值的滑动相关器。 在训练间隔期间，将这些相关峰值相加到通道轮廓存储器中。 对应于码字的相关峰值被加入到信道简档存储器中，并且与该码字的逆相对应的相关峰值在训练间隔期间被反转并添加到信道简档存储器中。 在训练间隔之后，确定间隔，由此将相关峰乘以信道简档存储器的内容的复共轭。 乘法结果在码字窗口间隔上累加以产生决策输出。

公开(公告)号：US20230146445A1

公开(公告)日：2023-05-11

申请号：US17515523

申请日：2021-10-31

Applicant: Redpine Signals, Inc.

Inventor： Martin KRAEMER ,  Ryan BOESCH ,  Wei XIONG

IPC: G06N3/063 ,  G06N3/04 ,  G06F7/544

CPC classification number: G06N3/0635 ,  G06F7/5443 ,  G06N3/04

Abstract: An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3 × 3 × 64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.

公开(公告)号：US20220417030A1

公开(公告)日：2022-12-29

申请号：US17359546

申请日：2021-06-26

Applicant: Redpine Signals, Inc.

Inventor： Ananya SHRIVASTAVA ,  Mohammed SUMAIR ,  Joydeep Kumar DEVNATH ,  Suyash Kandele ,  Govardhan Mattela

IPC: H04L9/32 ,  H04L9/30

Abstract: An unenrolled lightweight node is on a decentralized network with a trusted node and a plurality of peers. The unenrolled lightweight node and the peers run a lightweight blockchain consensus algorithm. The unenrolled lightweight node includes (a) circuitry for storing a token that includes a signature that includes at least a signature of at least a first identifier signed with a private key of the trusted node, the first identifier being associated with a public key of the unenrolled lightweight node, and (b) circuitry for broadcasting a request for blockchain enrollment of the unenrolled lightweight node to the plurality of peers. The authentication request including at least a second identifier that is associated with at least a public key of the unenrolled lightweight node, a signature created with at least the second identifier and a corresponding private key of the unenrolled lightweight node, and the token.

公开(公告)号：US20220382517A1

公开(公告)日：2022-12-01

申请号：US17335206

申请日：2021-06-01

Applicant: Redpine Signals, Inc.

Inventor： Martin KRAEMER ,  Ryan BOESCH ,  Wei XIONG

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/18

Abstract: A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values. The Gain Balanced AMAC has a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. In each of a series of multiply-accumulate cycles, the X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

公开(公告)号：US20220308888A1

公开(公告)日：2022-09-29

申请号：US17214805

申请日：2021-03-27

Applicant: Redpine Signals, Inc.

Inventor： Heonchul PARK

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments are provided for reduction of lost cycles after branch misprediction in multi-thread microprocessors. In some embodiments, a method includes fetching, by first stage circuitry of a multi-thread microprocessor, a pair of consecutive instructions of a program executed in a thread. The method also includes determining, by second stage circuitry of said microprocessor, during a clock cycle, that a first instruction in the pair is a branch instruction. The method further includes fetching, by the first stage circuitry, during a second clock cycle, a pair of branch target instructions of the program using a branch prediction, and determining, by third stage circuitry of said microprocessor, during the second clock cycle, that the branch prediction is a misprediction. The method still includes sending the second instruction to the second stage circuitry during a third clock cycle, and decoding the second instruction by the second stage circuitry during the third clock cycle.

公开(公告)号：US20220308887A1

公开(公告)日：2022-09-29

申请号：US17214802

申请日：2021-03-27

Applicant: Redpine Signals, Inc.

Inventor： Heonchul PARK

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments are provided for mitigation of branch misprediction penalty in hardware multi-thread microprocessors. In some embodiments, a hardware multi-thread microprocessor includes first stage circuitry that fetches a pair of consecutive instructions of a program executed in a thread. Such microprocessor also includes second stage circuitry that determines, during a clock cycle, that a first instruction in that pair is a branch instruction. The first stage circuitry fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction. Such microprocessor further includes third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle. The first stage circuitry sends the second instruction to the second stage circuitry during a third clock cycle after the second clock cycle. The second stage circuitry decodes the second instruction during the third clock cycle.