公开(公告)号：US06298100B1

公开(公告)日：2001-10-02

申请号：US09427315

申请日：1999-10-26

申请人： Aaron Reel Bouillet

发明人： Aaron Reel Bouillet

IPC分类号： H04L2714

CPC分类号： H04L27/066 ,  H04L2027/003 ,  H04L2027/0036 ,  H04L2027/0046 ,  H04L2027/0067

摘要： A receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information and a pilot component includes a carrier recovery network (22; FIG. 3) that produces a demodulated baseband signal. The carrier recovery network additionally responds to a locally generated control signal (Ph. Offset; 360) representing an unwanted phase offset of the pilot signal due to multipath distortion, for example. The control signal is used to compensate for the pilot phase offset before the demodulated signal is equalized. The control signal is produced by correlating received sync values with both a reference sync value (362) and a Hilbert transform of the reference sync value (363). The output of the carrier recovery network signal is phase compensated twice.

摘要翻译： 用于处理包含地面广播高分辨率电视信息和导频分量的VSB调制信号的接收机包括产生解调基带信号的载波恢复网络（22;图3）。 载波恢复网络还例如响应于表示由于多径失真导致的导频信号的不需要的相位偏移的本地产生的控制信号（Ph。Offset; 360）。 控制信号用于在解调信号相等之前补偿导频相位偏移。 通过将接收到的同步值与参考同步值（362）和参考同步值（363）的希尔伯特变换相关联来产生控制信号。 载波恢复网络信号的输出被相位补偿两次。

公开(公告)号：US06294992B1

公开(公告)日：2001-09-25

申请号：US09063752

申请日：1998-04-21

申请人： Kenneth L. Addy ,  Thomas P. Schmit ,  Patrick Adamo

发明人： Kenneth L. Addy ,  Thomas P. Schmit ,  Patrick Adamo

IPC分类号： G08B108

CPC分类号： H04L1/0057 ,  G08B25/007 ,  G08B25/10 ,  H04L1/24 ,  H04L27/066

摘要： A method, apparatus and system for maximizing transmission power levels in wireless security systems wherein the transmitted power is adjusted depending on the type of signal being transmitted in order to comply with power level restrictions imposed by agency regulations (e.g. Federal Communications Commission). Higher priority control signals messages are transmitted at the maximum permitted or normal output power level and are not compromised by the requirement for transmission of data signals that are transmitted at a reduced power level. In addition, a method and apparatus for reducing a required quantity of data signal transmissions in wireless security systems is provided, wherein data signals are exclusively transmitted at a reduced power level during an installation mode leaving only control signals to be transmitted at normal power during normal operation mode. Data information contained in the data signal is stored in a console during installation mode, and retrieved and displayed to the user in response to the control signal during normal operation mode. The reduction in data signal transmissions reduces on-air time, thereby reducing the potential for message clash.

摘要翻译： 一种用于使无线安全系统中的发射功率电平最大化的方法，装置和系统，其中所发送的功率根据所传输的信号的类型进行调节，以便符合由机构规定（例如联邦通信委员会）施加的功率电平限制。 较高优先级控制信号消息以最大允许或正常输出功率电平发送，并且不受传输以降低的功率电平发射的数据信号的要求的影响。 另外，提供了一种用于在无线安全系统中减少数据信号传输所需数量的方法和装置，其中数据信号在安装模式期间以降低的功率电平排他地传输，只留下正常功率期间正常发射的控制信号 操作模式。 包含在数据信号中的数据信息在安装模式下存储在控制台中，并且在正常操作模式期间响应于控制信号被检索并显示给用户。 数据信号传输的减少减少了空中时间，从而减少了消息冲突的可能性。

公开(公告)号：US6069524A

公开(公告)日：2000-05-30

申请号：US220785

申请日：1998-12-23

申请人： Victor G. Mycynek ,  Gary J. Sgrignoli

发明人： Victor G. Mycynek ,  Gary J. Sgrignoli

IPC分类号： H03L7/087 ,  H04L27/06 ,  H04L27/227

CPC分类号： H03L7/087 ,  H04L27/066

摘要： A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.

摘要翻译： FPLL具有I，Q和第三乘法器，I乘法器将解调信号提供给限幅器，Q乘法器向环路滤波器提供信号。 VCO和相移电路向I和Q乘法器提供正交信号。 模拟输入信号被施加到I乘法器和第三乘法器。 位于循环中的AC路径中的第三乘法器也被提供有限制器的数字输出，以避免由于杂散直流电压和电流引起的偏移的影响。 第三个乘法器将其输出提供给Q乘数。

公开(公告)号：US5825833A

公开(公告)日：1998-10-20

申请号：US594183

申请日：1996-01-31

申请人： Yoichi Sakaue

发明人： Yoichi Sakaue

IPC分类号： H03D7/16 ,  H03J7/08 ,  H04L27/06 ,  H04L27/00

CPC分类号： H03D7/16 ,  H03J7/08 ,  H04L27/066

摘要： A digital and analog reception apparatus includes a first mixer (MIX1) which converts up a reception signal having an input frequency fa inputted into an input terminal IN and a second mixer (MIX2) which converts down a first intermediate frequency fc of a signal outputted from the first mixer (MIX1) by using a second local frequency fd and a second intermediate frequency fe. The apparatus is also provided with a phase-locked loop (PLL), an automatic frequency controller (AFC) which comprises a second local oscillator and a low frequency band pass filter unit LPF adjusts a second local frequency fd, and a microcomputer discriminates an analog/digital distinction of the reception signal having the input frequency fa. Upon receiving an analog signal, the digital and analog reception apparatus deactivates a low-pass filter unit LPF, thereby having an AFC signal control a second local oscillator. On the other hand, upon reception of a digital signal, the phase-locked loop (PLL) and the low-pass filter unit LPF control the second local oscillator.

摘要翻译： 数字和模拟接收装置包括：第一混频器（MIX1），其将具有输入到输入端子IN的输入频率fa的接收信号转换为第二混频器（MIX2），第二混频器（MIX2）将从第 第一混频器（MIX1）通过使用第二本地频率fd和第二中频fe。 该装置还设置有锁相环（PLL），自动频率控制器（AFC），其包括第二本地振荡器和低频带通滤波器单元LPF调节第二本地频率fd，微机鉴别模拟 /具有输入频率fa的接收信号的数字区分。 在接收到模拟信号时，数字和模拟接收装置使低通滤波器单元LPF无效，从而使AFC信号控制第二本地振荡器。 另一方面，在接收到数字信号时，锁相环（PLL）和低通滤波器单元LPF控制第二本地振荡器。

公开(公告)号：US5818741A

公开(公告)日：1998-10-06

申请号：US632932

申请日：1996-04-16

申请人： Werner Boie ,  Michel Sonrier

发明人： Werner Boie ,  Michel Sonrier

IPC分类号： H03H21/00 ,  H03H17/02 ,  H04L27/06 ,  G06F17/10

CPC分类号： H04L27/066

摘要： The disclosure relates to a A digital filtering system of a signal, including a calculation circuit that calculates the average increase in amplitude .DELTA.X.sub.av (n) between two samples X(n), and an "output signal (Y(n)) circuit" that calculates a mean, weighted by a coefficient a, of the sample to be filtered X(n) and the previous sample Y(n-1) algebraically increased by said average increase in amplitude .DELTA.X.sub.av (n). The invention is applicable to digital signal processing.

摘要翻译： 本公开涉及一种信号的A数字滤波系统，包括计算电路，该计算电路计算两个采样X（n）和“输出信号（Y（n））电路之间的振幅DELTA Xav（n）的平均增加” 其计算由要滤波的样本X（n）的系数a加权的平均值，并且先前样本Y（n-1）通过所述平均增幅ΔTATA×AV（n）代数增加。 本发明适用于数字信号处理。

公开(公告)号：US4397039A

公开(公告)日：1983-08-02

申请号：US221151

申请日：1980-12-29

申请人： Gerald K. McAuliffe

发明人： Gerald K. McAuliffe

IPC分类号： H04L27/06 ,  H04B1/10 ,  H04B1/26

CPC分类号： H04L27/066

摘要： A receiver for demodulating a single sideband signal which is subject to rapid phase jitter employs a Hilbert splitter for obtaining the Hilbert transform of the single sideband signal, and a local oscillator for signal demodulation. A post-oscillator feedback loop instantaneously derives the amount of phase jitter in the single sideband signal, and employs the derived phase jitter to adjust the phase of the local oscillator so that the local oscillator tracks the single sideband signal.Instantaneous derivation of the phase jitter is obtained because all post-oscillator signal manipulations are algebraic; post-oscillator Hilbert transform generation is not required. A first embodiment derives the exact amount of phase jitter. A second embodiment, more simple than the first, derives the approximate amount of phase jitter.

摘要翻译： 用于解调受到快速相位抖动的单个边带信号的接收机采用希尔伯特分离器来获得单边带信号的希尔伯特变换和用于信号解调的本地振荡器。 后振荡器反馈环路瞬时导出单边带信号中的相位抖动量，并且采用导出的相位抖动来调整本地振荡器的相位，使得本地振荡器跟踪单个边带信号。 获得相位抖动的瞬时推导是因为所有后振荡器信号操作都是代数的; 不需要后振荡器希尔伯特变换生成。 第一实施例导出确切的相位抖动量。 第二实施例比第一实施例更简单，导出大致相位抖动量。

公开(公告)号：US4159527A

公开(公告)日：1979-06-26

申请号：US870647

申请日：1978-01-19

申请人： Haruki Yahata ,  Shunsuke Honda ,  Tadamichi Kawasaki

发明人： Haruki Yahata ,  Shunsuke Honda ,  Tadamichi Kawasaki

IPC分类号： G06F1/035 ,  H04L27/06 ,  H04L27/38 ,  G06F15/34 ,  H03B3/08

CPC分类号： H04L27/3818 ,  G06F1/0353 ,  H04L27/066

摘要： A periodic function wave generator is provided in a digital phase synchronizing circuit which comprises a memory circuit for storing the values of n phases obtained by equally dividing one period of a sine wave by 4n and each having a phase .theta.=90.degree./n(i+0.5), where n represents an integer and i is an integer of from 0 to n-1, a circuit for designating a predetermined one of these phases in one period, a circuit for converting an address read out of the memory circuit into one of the n phases in accordance with one of the ranges of 0.degree. to 90.degree., 90.degree. to 180.degree., 180.degree. to 270.degree. and 270.degree. to 360.degree. and a circuit for inverting the sign of the output of the memory circuit in accordance with the particular range in which the designated phase falls.

摘要翻译： 在数字相位同步电路中提供周期性函数波发生器，其包括存储电路，用于存储通过将正弦波的一个周期等于4n并且每个具有相位θ= 90°/ n（i +0.5），其中n表示整数，i是从0到n-1的整数，用于在一个周期中指定这些相位中的预定的一个的电路，用于将从存储器电路读出的地址转换成一个 根据0°至90°，90°至180°，180°至270°和270°至360°的范围之一的n相，并且用于将存储器电路的输出的符号反转的电路 根据指定相位落下的特定范围。

公开(公告)号：US4100495A

公开(公告)日：1978-07-11

申请号：US785693

申请日：1977-04-07

申请人： Angelo Luvison ,  Giancarlo Pirani

发明人： Angelo Luvison ,  Giancarlo Pirani

IPC分类号： H04L7/02 ,  H04L25/03 ,  H04L27/06 ,  H04L25/08

CPC分类号： H04L7/0062 ,  H04L25/03133 ,  H04L27/066

摘要： An incoming data stream in the output of a demodulator and its derivative in the output of a differentiator are passed by respective sampling gates to a pair of equalizers operating by recursive filtration. The optimized data pulses issuing from the first equalizer are quantized and, after storage in a shift register, are algebraically combined in a first adder with a reference signal x from that equalizer representing the vector sum of weighted data pulses from a succession of N preceding clock cycles; a resulting error signal e.sub.n is delivered to three cumulative multipliers forming part of three feedback loops which supply an optimized phase signal .zeta. to the demodulator, an optimized timing signal .tau. to the sampling gates and an optimized gain coefficient K to the equalizers. These three multipliers respectively receive the reference signal x from the first equalizer, an optimized differential signal dx/d.tau. from the second equalizer and an updating signal z from the first equalizer. A further cumulative multiplier forms part of a fourth feedback loop delivering an optimized channel coefficient G to the equalizers, this latter loop including a second adder which synthesizes another error signal e' from the incoming data pulses z and from the complex product G.multidot.x produced by the last-mentioned multiplier. Each feedback loop includes a selective delay circuit effective only during an operating phase, in contrast to an acquisition phase during which the first adder receives a locally generated test signal in lieu of the quantized data pulses.

摘要翻译： 解调器的输出中的输入数据流及其微分器的输出中的导数由相应的采样门传递到通过递归滤波操作的一对均衡器。 从第一均衡器发出的优化的数据脉冲被量化，并且在存储在移位寄存器中之后，在第一加法器中代数地组合来自该均衡器的参考信号x，该参考信号表示来自N个先前时钟的连续的加权数据脉冲的向量和 循环; 产生的误差信号en被递送到三个累积乘法器，其形成三个反馈回路的一部分，这三个反馈回路向解调器提供优化的相位信号zeta，对采样门提供优化的定时信号τ，并将优化的增益系数K提供给均衡器。 这三个乘法器分别从第一均衡器接收参考信号x，来自第二均衡器的优化差分信号dx / d tau和来自第一均衡器的更新信号z。 进一步的累积乘数形成第四反馈环路的一部分，其向均衡器提供优化的信道系数G，后一循环包括第二加法器，其从进入的数据脉冲z和从复数乘积Gxx产生的复合乘积Gxx合成另一个误差信号e' 最后提到的乘数。 每个反馈回路包括仅在操作阶段有效的选择性延迟电路，与第一加法器接收代替量化的数据脉冲的本地生成的测试信号的获取阶段相反。

公开(公告)号：USRE28638E

公开(公告)日：1975-12-02

申请号：US50892774

申请日：1974-09-25

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L27/06

CPC分类号： H04L27/066 ,  H04L7/0058 ,  H04L7/0331 ,  H04L25/0305

摘要： The invention is directed to an improvement in a digital data receiver of the type which utilizes an adaptive equalizer having a plurality of adjustable attenuators to remove distortion in received signals. The improvement comprises a system which utilizes the signals available at the equalizer adjustable attenuators to achieve accurate and stable carrier phase and timing control signals.

公开(公告)号：US3909752A

公开(公告)日：1975-09-30

申请号：US44000574

申请日：1974-02-06

申请人： RIXON

发明人： STUART RICHARD L

IPC分类号： G08B29/18 ,  H04L27/06 ,  H04B3/04

CPC分类号： H04L27/066 ,  G08B29/181

摘要： A carrier phase correction circuit for a data communications system is provided which includes an automatic transversal equalizer and which utilizes the voltage control signals that are connected to the attenuators for the two taps adjacent to the central tap of the transversal equalizer, which signals are used in equalizing the baseband input to the equalizer. The two signals are compared and a first output produced when one of the signals is greater and a second output produced when the second is greater, the two outputs being used in controlling advancing and retarding the recovered carrier phase.

摘要翻译： 提供了一种用于数据通信系统的载波相位校正电路，其包括自动横向均衡器，并利用连接到与横向均衡器的中心抽头相邻的两个抽头的衰减器的电压控制信号，该信号用于 将基带输入均衡到均衡器。 比较两个信号，并且当信号中的一个较大时产生第一输出，并且当第二信号较大时产生第二输出，两个输出用于控制提前和延迟恢复的载波相位。