利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.015 秒)

    FPLL with third multiplier in an analog input signal
    3.
    发明授权
    FPLL with third multiplier in an analog input signal 有权
    FPLL在FPLL中的交流路径中具有第三乘法器，并提供模拟输入信号

    公开(公告)号：US6069524A

    公开(公告)日：2000-05-30

    申请号：US220785

    申请日：1998-12-23

    申请人： Victor G. Mycynek ,  Gary J. Sgrignoli

    发明人： Victor G. Mycynek ,  Gary J. Sgrignoli

    IPC分类号： H03L7/087 ,  H04L27/06 ,  H04L27/227

    CPC分类号： H03L7/087 ,  H04L27/066

    摘要： A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.

    摘要翻译： FPLL具有I，Q和第三乘法器，I乘法器将解调信号提供给限幅器，Q乘法器向环路滤波器提供信号。 VCO和相移电路向I和Q乘法器提供正交信号。 模拟输入信号被施加到I乘法器和第三乘法器。 位于循环中的AC路径中的第三乘法器也被提供有限制器的数字输出，以避免由于杂散直流电压和电流引起的偏移的影响。 第三个乘法器将其输出提供给Q乘数。

    AGC system with overriding, maximum gain during an initial interval to enhance signal acquisition
    5.
    发明授权
    AGC system with overriding, maximum gain during an initial interval to enhance signal acquisition 失效
    AGC系统具有覆盖，初始间隔期间的最大增益，以增强信号采集

    公开(公告)号：US5546138A

    公开(公告)日：1996-08-13

    申请号：US320362

    申请日：1994-10-11

    申请人： Gopalan Krishnamurthy ,  Victor G. Mycynek ,  Gary J. Sgrignoli

    发明人： Gopalan Krishnamurthy ,  Victor G. Mycynek ,  Gary J. Sgrignoli

    IPC分类号： H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/52

    CPC分类号： H04N5/52 ,  H03G3/3052 ,  H03G3/3078 ,  H04N5/4401 ,  H04N5/455

    摘要： A dual mode AGC system for a television receiver in which data is in the form of symbols occurring at a fixed symbol rate. The symbols are sent in successive data segments, each having a sync character. Enablement of an AFC Defeat signal defines an initial interval during which the IF gain is maximum. When the AFC Defeat signal becomes inactive, the receiver is operated in a non-coherent mode in which the gain of the IF amplifier is reduced incrementally whenever the IF signal exceeds a clipping level for a period of eight successive symbol clocks. Upon a segment sync lock condition occurring, a normal coherent mode is entered in which the AGC responds to a signal characteristic, i.e. data segment sync. The rate of gain change available in the non-coherent mode-is much greater than that in the normal coherent mode.

    摘要翻译： 一种用于电视接收机的双模AGC系统，其中数据是以固定符号速率发生的符号的形式。 符号在连续的数据段中发送，每个段具有同步字符。 启用AFC失败信号定义了IF增益最大的初始间隔。 当AFC失败信号变为无效时，接收机在非相干模式下操作，其中每当IF信号在八个连续符号时钟周期内超过限幅电平时，IF放大器的增益逐渐减小。 在发生段同步锁定条件时，进入正常相干模式，其中AGC响应于信号特性，即数据段同步。 在非相干模式下可用的增益变化率远远大于正常相干模式。

    Bandwidth stabilized PLL
    6.
    发明授权
    Bandwidth stabilized PLL 有权
    带宽稳定的PLL

    公开(公告)号：US06590950B1

    公开(公告)日：2003-07-08

    申请号：US09255059

    申请日：1999-02-22

    申请人： Victor G. Mycynek

    发明人： Victor G. Mycynek

    IPC分类号： H03D324

    CPC分类号： H03D3/245

    摘要： A bandwidth stabilized PLL in an FPLL has an I channel including an I channel signal, having a pilot, and a Q channel signal. The DC offset, including the pilot, of the I channel signal is determined. The value of the pilot is found by subtracting the determined DC offset from the I channel signal. An error signal is developed from the known value of the transmitted pilot and the determined value of the pilot. The error signal is used to control a gain block for the Q channel for stabilizing the bandwidth of the PLL. Different embodiments are shown for controlling the gain of the PLL from both inside and outside of the PLL.

    摘要翻译： FPLL中的带宽稳定的PLL具有包括具有导频的I信道信号和Q信道信号的I信道。 确定I信道信号的包括导频的DC偏移。 通过从I信道信号中减去所确定的DC偏移来找到导频的值。 从所发射的导频的已知值和导频的确定值产生误差信号。 误差信号用于控制Q通道的增益块，以稳定PLL的带宽。 示出了用于从PLL的内部和外部控制PLL的增益的不同实施例。

    Current mode AGC system for television tuner
    7.
    发明授权
    Current mode AGC system for television tuner 失效
    电视调谐器的电流模式AGC系统

    公开(公告)号：US5575003A

    公开(公告)日：1996-11-12

    申请号：US354406

    申请日：1994-12-12

    申请人： Victor G. Mycynek

    发明人： Victor G. Mycynek

    IPC分类号： H03G3/30 ,  H04N5/52 ,  H04B1/06

    CPC分类号： H04N5/52 ,  H03G3/3068

    摘要： The tuner-IF system operates with three current mirrors. One current mirror accepts an AGC signal and develops an RF AGC voltage, another current mirror accepts the AGC signal and develops an IF AGC voltage and a third current mirror establishes a minimum IF gain for the system and allows for additional slight IF gain reduction for excessive incoming signals. The three current mirrors are of the Wilson type and enable flexibility in establishing crossover points, delay times between the tuner RF and IF gain reductions and the like.

    摘要翻译： 调谐器 - 中频系统采用三个电流镜。 一个电流镜接受AGC信号并产生RF AGC电压，另一个电流镜接受AGC信号并产生IF AGC电压，而第三电流镜为系统建立最小的IF增益，并允许额外轻微的IF增益降低 传入信号。 三个电流镜是威尔逊型，并且能够灵活地建立交叉点，调谐器RF和IF增益减小之间的延迟时间等。

    Compensated inverting/noninverting differential amplifier
    8.
    发明授权
    Compensated inverting/noninverting differential amplifier 失效
    补偿反相/同相差分放大器

    公开(公告)号：US4536717A

    公开(公告)日：1985-08-20

    申请号：US538291

    申请日：1983-10-03

    申请人： Raymond C. Hauge ,  Victor G. Mycynek

    发明人： Raymond C. Hauge ,  Victor G. Mycynek

    IPC分类号： H03F1/32 ,  H03F1/34 ,  H03F3/45

    CPC分类号： H03F1/34 ,  H03F1/3211 ,  H03F3/45071

    摘要： A linear gain differential amplifier having feedback stabilization which is capable of providing inverted and noninverted outputs of equal amplitude is disclosed. A pair of coupled voltage following, feedback stabilized amplifier circuits provide a differential output which is a function of only the respective input signals and the passive component values in the circuit. The present invention is capable of operating at high frequencies over a wide bandwidth and is particularly adapted for video signal processing where linear gain, DC stability, phase compensation and high frequency response are required in order to prevent video luminance and chrominance fluctuations caused by differential gain and phase distortion. More specifically, the present invention is particularly adapted for use as a compensated inverting/noninverting differential amplifier such as employed in a subscription television system encoder, a full wave precision rectifier, or in any application requiring a high performance differential amplifier.

    摘要翻译： 公开了一种具有反馈稳定性的线性增益差分放大器，其能够提供相等振幅的反相和非反相输出。 一对耦合电压跟随，反馈稳定的放大器电路提供差分输出，该差分输出仅是电路中相应的输入信号和无源分量值的函数。 本发明能够在宽带宽的高频下工作，特别适用于需要线性增益，直流稳定性，相位补偿和高频响应的视频信号处理，以防止由差分增益引起的视频亮度和色度波动 和相位失真。 更具体地说，本发明特别适合用作补偿反相/同相差分放大器，例如在订阅电视系统编码器，全波精密整流器中或在需要高性能差分放大器的任何应用中使用。

    Noise processing system for a television receiver
    9.
    发明授权
    Noise processing system for a television receiver 失效
    电视接收机的噪声处理系统

    公开(公告)号：US4377823A

    公开(公告)日：1983-03-22

    申请号：US249793

    申请日：1981-04-01

    申请人： Victor G. Mycynek

    发明人： Victor G. Mycynek

    IPC分类号： H04N5/213 ,  H04N5/08 ,  H04N5/21

    CPC分类号： H04N5/213

    摘要： A noise processing system is described for use in protecting a television receiver's sync processing path and its video processing path from impulse noise. To protect the video processing path, a first noise canceller receives a composite video signal, detects each noise pulse therein which exceeds a video noise threshold, and replaces each such noise pulse with a selected voltage level. The resultant noise processed video may then be applied to the receiver's video processing path. To protect the sync processing path, another noise canceller receives the composite video signal, detects noise pulses therein which exceed a sync noise threshold, generates a detection pulse for each such noise pulse, and combines the detection pulses with composite video so as to cancel the noise pulses. Thus, another noise processed video signal is developed for application to the receiver's sync processing path.

    摘要翻译： 描述了用于保护电视接收机的同步处理路径及其视频处理路径免受脉冲噪声的噪声处理系统。 为了保护视频处理路径，第一噪声消除器接收复合视频信号，检测其中超过视频噪声阈值的每个噪声脉冲，并且用所选择的电压电平替换每个这样的噪声脉冲。 然后将所得到的噪声处理视频应用于接收机的视频处理路径。 为了保护同步处理路径，另一个噪声消除器接收复合视频信号，检测超过同步噪声阈值的噪声脉冲，产生每个这样的噪声脉冲的检测脉冲，并组合检测脉冲与复合视频，以消除 噪声脉冲。 因此，开发另一噪声处理视频信号以应用于接收机的同步处理路径。

    VSB reset to minimize data loss
    10.
    发明授权
    VSB reset to minimize data loss 有权
    VSB复位以最小化数据丢失

    公开(公告)号：US06686972B1

    公开(公告)日：2004-02-03

    申请号：US09516219

    申请日：2000-03-01

    申请人： Victor G. Mycynek

    发明人： Victor G. Mycynek

    IPC分类号： H04N5445

    CPC分类号： H04L27/06 ,  H03G3/3052 ,  H04N5/4401 ,  H04N5/50 ,  H04N5/52

    摘要： A receiver for VSB signals includes tuner channel changing circuitry. AGC circuitry, an IF FPLL and confidence counters, for indicating when signal acquisition or loss occurs. When a loss of signal indication is generated, the IF FPLL is reset, but not the tuner channel changing circuitry and the AGC circuitry, in order to quickly reacquire the signal. If the loss of signal indication persists for a predetermined time or for a predetermined number of loss of signal indications, the IF FPLL, the tuner channel changing circuitry and the AGC circuitry are all reset to reacquire the signal.

    摘要翻译： 用于VSB信号的接收机包括调谐器通道改变电路。 AGC电路，IF FPLL和置信计数器，用于指示何时发生信号采集或丢失。 当产生信号指示丢失时，IF FPLL被复位，而不是调谐器通道改变电路和AGC电路，以便快速重新获取信号。 如果信号指示的丢失持续了预定时间或预定数量的信号指示丢失，则IF FPLL，调谐器通道改变电路和AGC电路都被重置以重新获取信号。