公开(公告)号：US20040088631A1

公开(公告)日：2004-05-06

申请号：US10642546

申请日：2003-08-15

发明人： Jurgen Blank

IPC分类号： H04L001/00 ,  G06F011/00 ,  G06F011/30 ,  H03M013/00 ,  G08C025/00

CPC分类号： H04L41/0677 ,  G01R31/3185 ,  H04L25/08

摘要： A method and a configuration produce a fault signal that is suitable for identifying transmission faults when using differential signaling. A first mid-level signal whose potential is in the area of the mid-point between the signal level on a first signal line and a signal level on a second signal line, when a logic null1null is transmitted is compared with a second mid-level signal formed when a logic null0null is transmitted. The fault signal is produced if the discrepancy between the two mid-level signals is greater than a predetermined threshold value.

摘要翻译： 一种方法和配置产生一种适用于在使用差分信号时识别传输故障的故障信号。 当发送逻辑“1”时，第一中间信号的电位在第一信号线上的信号电平和第二信号线上的信号电平之间的中点的区域中与第二中间信号 当发送逻辑“0”时形成的级信号。 如果两个中间信号之间的差异大于预定阈值，则产生故障信号。

公开(公告)号：US20040083419A1

公开(公告)日：2004-04-29

申请号：US10431459

申请日：2003-05-08

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Osamu Chiba ,  Yoshifumi Azekawa

IPC分类号： H03M013/00 ,  H04L001/00 ,  G06F011/00 ,  G08C025/00

CPC分类号： H03M7/20

摘要： A disparity signal and a 6-bit subblock are provided to a 5B/6B decoding part, and a decoded data, a disparity signal, and an error candidate signal are outputted from the 5B/6B decoding part. The disparity signal and a 4-bit subblock are provided to a 3B/4B decoding part, and a decoded data, a disparity signal, and an error candidate signal are outputted from the 3B/4B decoding part. A data hold circuit delays the disparity signal by one clock and then provides the resulting signal to the 5B/6B decoding part. At least part of the decoding processing in the 3B/4B decoding part is executed in parallel with the obtaining of the disparity signal in the 5B/6B decoding part.

摘要翻译： 视差信号和6位子块被提供给5B / 6B解码部分，并且从5B / 6B解码部分输出解码数据，视差信号和错误候选信号。 视差信号和4位子块被提供给3B / 4B解码部分，并且解码数据，视差信号和错误候选信号从3B / 4B解码部分输出。 数据保持电路将视差信号延迟一个时钟，然后将得到的信号提供给5B / 6B解码部分。 与5B / 6B解码部中的视差信号的获取并行地执行3B / 4B解码部的解码处理的至少一部分。

公开(公告)号：US20040054961A1

公开(公告)日：2004-03-18

申请号：US10246378

申请日：2002-09-17

发明人： Ajay K. Dubey ,  Herve Bleunven

IPC分类号： H04L001/00 ,  G06F011/00 ,  H03M013/00 ,  G08C025/00

CPC分类号： H04L1/0063 ,  H03M13/09 ,  H04J3/14 ,  H04J2203/006 ,  H04J2203/0096 ,  H04L2001/0094

摘要： A path parity error signal may be calculated by determining an inputted payload signal, determining a memory state, determining a previous path parity signal, determining a previous master signal, and relating them.

摘要翻译： 可以通过确定输入的有效载荷信号，确定存储器状态，确定先前的路径奇偶校验信号，确定先前的主信号并将它们相关联来计算路径奇偶校验错误信号。

公开(公告)号：US20030237037A1

公开(公告)日：2003-12-25

申请号：US10175196

申请日：2002-06-19

申请人： Koninklijke Philips Electronics N.V.

发明人： Aravind Soundararajan

IPC分类号： H04L001/00 ,  G06F011/00 ,  G06F011/30 ,  H03M013/00 ,  G08C025/00 ,  H04L001/18 ,  G08C025/02

CPC分类号： H04B17/0085 ,  H04B17/23

摘要： A method and system for ascertaining the accuracy of transmission of a test signal. A first transceiver device transmits the test signal to a second transceiver device. The first transceiver device is wireless. The second transceiver device receives and retransmits the test signal back to the first transceiver device, without manual intervention by a user of the second transceiver device. The first transceiver device may additionally determine a measure of an extent to which the retransmitted signal differs from the test signal, and display the measure so determined.

摘要翻译： 一种用于确定测试信号的传输精度的方法和系统。 第一收发器装置将测试信号发送到第二收发器装置。 第一个收发器设备是无线的。 第二收发器设备接收并将测试信号重发回到第一收发器设备，而无需第二收发器设备的用户的手动干预。 第一收发器装置还可以确定重发信号与测试信号不同的程度的度量，并显示如此确定的度量。

公开(公告)号：US20030192000A1

公开(公告)日：2003-10-09

申请号：US10118271

申请日：2002-04-08

申请人： Harris Corporation

发明人： David Kenyon Vail ,  Stephen S. Wilson ,  Jeffrey D. Volz ,  Joshua P. Bruckmeyer ,  Allen G. Plum

IPC分类号： G06K005/04 ,  H04L001/00 ,  G06F011/00 ,  G06F011/30 ,  H03M013/00 ,  G08C025/00

CPC分类号： G06F11/2007 ,  G06F11/2005

摘要： A communications system may include a plurality of communications buses, at least one bus device connected to the plurality of communications buses, and a plurality of bus controllers for sending a plurality of bus enable signals to the at least one bus device. The at least one bus device may include selection circuitry for selecting one of the communications buses based upon the plurality of bus enable signals while being tolerant of an error on at least one of the bus enable signals. First and second bus enable signals may have a same value and may be generated by a primary bus controller upon receiving power. A third bus enable signal may be generated by a redundant bus controller upon receiving power.

摘要翻译： 通信系统可以包括多个通信总线，连接到多个通信总线的至少一个总线设备，以及用于向多个总线设备发送多个总线使能信号的多个总线控制器。 至少一个总线设备可以包括选择电路，用于基于多个总线使能信号来选择通信总线之一，同时容忍至少一个总线使能信号上的错误。 第一和第二总线使能信号可以具有相同的值，并且可以在接收电力时由主总线控制器产生。 在接收电力时，冗余总线控制器可以产生第三总线使能信号。

公开(公告)号：US20030172340A1

公开(公告)日：2003-09-11

申请号：US10238984

申请日：2002-09-09

发明人： Hiroshi Nozawa ,  Shinzo Koyama ,  Masao Takayama ,  Yoshikazu Fujimori

IPC分类号： H04L001/00 ,  G06F011/00 ,  G06F011/30 ,  H03M013/00 ,  G08C025/00 ,  G11C029/00

CPC分类号： G11C7/1006

摘要： A coding-decoding device and a coding-decoding method that take less time for coding and decoding are provided while using less number of logic gates. A memory device 15 substantially stores b pieces of conversion logic equations produced with a conversion logic equation producing device 13. An operation device 17 has a programmable hardware logic circuit to constitute logics sequentially according to plural execution unit logic equations obtained by dividing b pieces of conversion logic equations stored in the memory device 15 into execution units for respective execution unit logic equations using the hardware logic circuit. Besides, the operation device 17 sequentially divides and calculates the second sentences from the first sentences according to the constituted logics. An output device 19 collects and outputs the second sentences calculated with the operation device 17

摘要翻译： 在使用较少数量的逻辑门的同时，提供了编码解码装置和编码解码方法，其中编码解码时间较短。 存储装置15基本上存储由转换逻辑方程产生装置13产生的b个转换逻辑方程式。操作装置17具有可编程硬件逻辑电路，以根据多个执行单位逻辑方程顺序地构成逻辑， 存储在存储器装置15中的逻辑方程变成使用硬件逻辑电路的执行单元逻辑方程的执行单元。 此外，操作装置17根据构成的逻辑顺序地分割和计算来自第一句子的第二句子。 输出装置19收集并输出用操作装置17计算的第二句子

公开(公告)号：US20030149927A1

公开(公告)日：2003-08-07

申请号：US09805899

申请日：2001-03-15

发明人： Seongmoon Wang

IPC分类号： G01R031/28 ,  G06F011/00 ,  H04L001/00 ,  H03M013/00 ,  G08C025/00

CPC分类号： G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F11/263

摘要： Techniques for generating a test set for hard to detect faults is disclosed. A set of hard to detect faults is identified. A test set for the hard to detect faults is generated by using an improved automatic test pattern generator. The improved automatic test pattern generator is adapted to consider hardware overhead and test sequence lengths, the hardware overheads being incurred when each new testcube is added to the test set. Parallel and serial type test per scan built-in self test circuits designed and adapted to use the disclosed improved automatic test pattern generator are also disclosed.

摘要翻译： 公开了用于生成难以检测故障的测试装置的技术。 确定了一组难以检测的故障。 通过使用改进的自动测试模式发生器产生难以检测故障的测试集。 改进的自动测试模式生成器适用于考虑硬件开销和测试序列长度，当将每个新的测试器添加到测试集中时，会​​产生硬件开销。 还公开了并行和串联型测试，每个扫描内置的自检电路设计并适用于使用所公开的改进的自动测试图案发生器。

公开(公告)号：US20030145274A1

公开(公告)日：2003-07-31

申请号：US10347524

申请日：2003-01-21

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-hee Hwang ,  Yoon-woo Lee ,  Sung-hyu Han ,  Sang-hyun Ryu ,  Young-im Ju

IPC分类号： G06F011/00 ,  H04L001/00 ,  H03M013/00 ,  G08C025/00

CPC分类号： H04L1/0082 ,  G11B20/1833 ,  H03M13/47 ,  H04L1/0057

摘要： A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction, indicating in error flags the remaining code words except at least some code words from code words having uncorrectable errors, and performing error correction on code words in the other direction based on the error flags. Accordingly, errors that have been conventionally considered as being uncorrectable may now be corrected.

摘要翻译： 解码方法和装置通过对从​​行方向和列方向选择的一个方向上的纠错码块的码字执行纠错来进行操作，指示除代码字以外的至少一些码字之外的剩余码字 具有不可校正的错误，并且基于错误标志对另一方向上的码字执行纠错。 因此，现在可以校正以前被认为是不可校正的错误。

公开(公告)号：US20030131302A1

公开(公告)日：2003-07-10

申请号：US10347243

申请日：2003-01-21

发明人： Robert van Nobelen

IPC分类号： H04L001/00 ,  G06F011/00 ,  G06F011/30 ,  H03M013/00 ,  G08C025/00

CPC分类号： H04L1/1607 ,  H04L1/1812 ,  H04L1/1819

摘要： A method and apparatus for sending blocks of data without any error correcting coding is described. If the block is received without an error then the next block of data is transmitted. If the block is received with an error, the receiving device sends a message requesting error correcting information. The transmitting device sends the error correcting information in specified increments until the receiving device can successfully decode the block without error. Once the block is received without errors, the next block of data is transmitted.

公开(公告)号：US20030115540A1

公开(公告)日：2003-06-19

申请号：US10288910

申请日：2002-11-06

发明人： Jae-Hwui Bae ,  Jae-Hyun Seo ,  Seung Won Kim ,  Chieteuk Ahn

IPC分类号： H04L001/00 ,  G06F011/00 ,  G06F011/30 ,  H03M013/00 ,  G08C025/00 ,  H03M013/03

CPC分类号： H04L1/006 ,  H03M13/253 ,  H03M13/256 ,  H03M13/2936 ,  H03M13/6538

摘要： A baseband encoding apparatus and frequency modulation method using the same in vestigial sideband (VSB) transmission system is disclosed. The apparatus includes a trellis encoder having a 1/2 code rate for generating a 2-bit output signal based on a 1-bit input signal and generating 4 types of signal levels in baseband by using the 2-bit output signal for converting the 4 types of the signal levels of the trellis encoder to symbols and generating 4 types of output symbols. The present invention can improve the receiving performance of the VSB transmission system in a mobile environment by implementing the trellis coded modulation having 1/2 code rate in the VSB broadcasting transmission system, which critically decreases minimum signal-to-noise ratio for recovering an original signal.

摘要翻译： 公开了一种在残留边带（VSB）传输系统中使用该基带编码装置和频率调制方法的基带编码装置和频率调制方法。 该装置包括格码编码器，其具有1/2码率，用于基于1位输入信号产生2位输出信号，并通过使用2位输出信号在基带中产生4种类型的信号电平，以转换4位 网格编码器的信号级别类型到符号并生成4种类型的输出符号。 本发明可以通过在VSB广播传输系统中实现具有1/2码率的网格编码调制来改善移动环境中的VSB传输系统的接收性能，这严重降低了用于恢复原始数据的最小信噪比 信号。