公开(公告)号：US20220239539A1

公开(公告)日：2022-07-28

申请号：US17722048

申请日：2022-04-15

Applicant: STMICROELECTRONICS SA

Inventor： Fatima BARRAMI

IPC: H04L27/26 ,  H04L27/20 ,  H04B10/548 ,  H04B10/69

Abstract: An OFDM (orthogonal frequency division multiplexing) transmitter includes an inverse fast Fourier transform circuit, which, in operation, generates, based on digital input data, a complex time-varying digital signal having real and imaginary components; and a multiplexer adapted to generate a time-multiplexed digital signal by time-multiplexing one or more of the real components with one or more of the imaginary components.

公开(公告)号：US20220199648A1

公开(公告)日：2022-06-23

申请号：US17544665

申请日：2021-12-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier WEBER ,  Christophe LECOCQ

IPC: H01L27/12 ,  H01L27/02 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

公开(公告)号：US11353508B2

公开(公告)日：2022-06-07

申请号：US17031713

申请日：2020-09-24

Applicant: STMICROELECTRONICS SA

Inventor： Ricardo Gomez Gomez

IPC: G01R31/3185 ,  G01R31/3177 ,  G06F11/267 ,  G06F11/16 ,  G06F11/18 ,  G01R31/3181

Abstract: A method tests a plurality of devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices. The test data in the test chains of the devices is shifted forward by one position. The shifting includes writing test data in the last position of a test chain to a first position in the test chain. The comparing and the shifting are repeated until the test data in the last position of each test chain when the testing is started is shifted back into the last position of the respective test chain. The plurality of devices may have a same structure and a same functionality.

公开(公告)号：US20220160314A1

公开(公告)日：2022-05-26

申请号：US17529543

申请日：2021-11-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Gilles GASIOT ,  Severin TROCHUT ,  Olivier LE NEEL ,  Victor MALHERBE

IPC: A61B6/00 ,  G01T1/24

Abstract: An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.

公开(公告)号：US20220099718A1

公开(公告)日：2022-03-31

申请号：US17421801

申请日：2019-01-22

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS) ,  STMICROELECTRONICS SA ,  UNIVERSITE DE BORDEAUX ,  INSTITUT POLYTECHNIQUE DE BORDEAUX

Inventor： Vincent Knopik ,  Jeremie Forest ,  Eric Kerherve

IPC: G01R25/04 ,  H04B17/21

Abstract: The method for detecting the phase (Φ1) of an analog signal (SA1) via a hybrid coupler (CH1) operating in a power-combiner mode, the hybrid coupler (CH1) comprising a first input (BE1) intended to receive the analog signal (SA1), a second input (BE2) intended to receive a reference signal (SREF) having a reference phase (Φ2) and the same frequency (FREF) as the analog signal (SA1), and two outputs (BS1, BS2), and configured to generate, at these two outputs (BS1, BS2), a first output signal (SS1) and a second output signal (SS2), respectively, comprises measuring peak values (A1, A2, A3, A4) of the analog signal (SA1), of the reference signal (SREF), and of at least one of the first and second output signals (SS1, SS2), calculating the phase shift (Φ1-Φ2) between the phase (Φ1) of the analog signal and the reference phase (Φ2) depending on said measured peak values (A1, A2, A3, A4), and determining the phase (Φ1) of the analog signal (SA1) depending on said calculated phase shift (Φ1-Φ2) and the reference phase (Φ2).

公开(公告)号：US11269140B2

公开(公告)日：2022-03-08

申请号：US16185654

申请日：2018-11-09

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert Manouvrier ,  Jean-Francois Carpentier ,  Patrick LeMaitre

IPC: G02B6/124 ,  G02B6/30 ,  G02F1/025 ,  G02B6/293

Abstract: An electro-optic device may include a photonic chip having an optical grating coupler at a surface. The optical grating coupler may include a first semiconductor layer having a first base and first fingers extending outwardly from the first base. The optical grating coupler may include a second semiconductor layer having a second base and second fingers extending outwardly from the second base and being interdigitated with the first fingers to define semiconductor junction areas, with the first and second fingers having a non-uniform width. The electro-optic device may include a circuit coupled to the optical grating coupler and configured to bias the semiconductor junction areas and change one or more optical characteristics of the optical grating coupler.

公开(公告)号：US11250930B2

公开(公告)日：2022-02-15

申请号：US16709019

申请日：2019-12-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Rousset) SAS

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C17/00 ,  G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US11250309B2

公开(公告)日：2022-02-15

申请号：US15694510

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/04 ,  G06N3/063 ,  H01L27/02 ,  G11C11/54 ,  H01L29/423 ,  H03K3/356

Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

公开(公告)号：US20220013654A1

公开(公告)日：2022-01-13

申请号：US17486000

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11223386B2

公开(公告)日：2022-01-11

申请号：US16878084

申请日：2020-05-19

Applicant: STMicroelectronics SA

Inventor： Mohammed Tmimi ,  Philippe Galy

IPC: H04B3/02 ,  H04L27/20

Abstract: Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.