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    SET OF INTEGRATED STANDARD CELLS
    1.
    发明申请
    SET OF INTEGRATED STANDARD CELLS 有权

    公开(公告)号：US20220199648A1

    公开(公告)日：2022-06-23

    申请号：US17544665

    申请日：2021-12-07

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Olivier WEBER ,  Christophe LECOCQ

    IPC: H01L27/12 ,  H01L27/02 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238

    Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

    STRAINED TRANSISTORS AND PHASE CHANGE MEMORY
    3.
    发明公开
    STRAINED TRANSISTORS AND PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20230329008A1

    公开(公告)日：2023-10-12

    申请号：US18335940

    申请日：2023-06-15

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Remy BERTHELON ,  Olivier WEBER

    IPC: H10B63/00

    CPC classification number: H10B63/32 ,  H10B63/80

    Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

    ELECTRONIC DEVICE MANUFACTURING METHOD
    4.
    发明公开
    ELECTRONIC DEVICE MANUFACTURING METHOD 审中-公开

    公开(公告)号：US20230411450A1

    公开(公告)日：2023-12-21

    申请号：US18330287

    申请日：2023-06-06

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Remy BERTHELON ,  Olivier WEBER

    IPC: H01L29/06 ,  H01L21/762 ,  H01L21/321

    CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L21/3212 ,  H10B63/10

    Abstract: The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.

    STRAINED TRANSISTORS AND PHASE CHANGE MEMORY
    6.
    发明申请
    STRAINED TRANSISTORS AND PHASE CHANGE MEMORY 有权

    公开(公告)号：US20210343788A1

    公开(公告)日：2021-11-04

    申请号：US17244514

    申请日：2021-04-29

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Remy BERTHELON ,  Olivier WEBER

    IPC: H01L27/24

    Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

    METHOD OF FABRICATING AN ELECTRONIC CHIP INCLUDING A MEMORY CIRCUIT
    7.
    发明公开
    METHOD OF FABRICATING AN ELECTRONIC CHIP INCLUDING A MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20240147737A1

    公开(公告)日：2024-05-02

    申请号：US18491349

    申请日：2023-10-20

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Olivier WEBER ,  Remy BERTHELON

    IPC: H10B63/00 ,  H10B63/10

    CPC classification number: H10B63/32 ,  H10B63/10 ,  H10B63/80

    Abstract: A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.

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