摘要:
The discovery and configuration of devices of interest connected to the Ethernet by an Ethernet port is disclosed. To perform discovery, Client software in a management interface transmits packets including the address of the management interface and a port identifier to a known broadcast address, requesting the MAC address for all devices of interest. Server software in the devices of interest parse the broadcast packets and broadcast a packet containing a MAC address that uniquely identifies the devices of interest back to the Client. Once the MAC addresses are returned to the Client, the Client can then broadcast protocol packets requesting the configuration of a specific device of interest such as a new IP address. Once a device of interest is configured with at least an IP address, the device of interest can communicate using TCP/IP, and it can thereafter be managed using higher level tools and firmware.
摘要:
The synchronization of trunk failover between two FC-AL switches when a primary trunk failure occurs is disclosed. If primary trunk T1 should fail, S1 bypasses the cascade port and sends a MaRK (MRK) ordered set out over duplicate trunk T2 to switch S2. In response, S2 sends an acknowledgement MRK ordered set over T2 back to S1. S1 then reconfigures the switch to establish T2 as the primary trunk, and acts as a masters in the failover process and initiates LIP ordered sets which are communicated to all devices in the system to initialize them. Note that when S2 receives the MRK ordered set and acknowledges it by sending an acknowledgement MRK back to S1, it acts as a slave in the failover process and does not attempt to initiate LIPs, thereby eliminating the possibility of multiple Loop Initialization cycles and reducing the time in which data cannot be transmitted.
摘要:
Methods and apparatus for switching Fiber Channel Arbitrated Loop Systems is provided between a plurality of Fiber Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS. In yet other aspects, the system ensures device access fairness through one or more techniques, including a rotating priority system, a counter to count the number of OPNs, especially sequential OPNs, and/or priority based on port type. Device zoning may be implemented. In one implementation, the system includes trunking such that frames may be transferred on multiple ports.
摘要:
Embodiments of the present invention provide for an IOC that does not limit each CPU to a particular port. Instead, the IOC may allow each CPU to communicate with all ports. Thus, the IOC can process CPU communications to determine which port to send them to, and send them to the correct port as well as process incoming communications from the ports to determine which CPU to send them to and send these communications to the correct CPU. This may significantly increase the flexibility and efficiency of a storage network.
摘要:
Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.
摘要:
Embodiments of the present invention provide for creating and using persistent connections in SAS networks. A persistent connection may be a connection that persists for longer than the usual SAS connection. More specifically, it is a connection that is not subject to periodic tear downs by SAS devices according to existing SAS protocols (such as, by using CLOSE or BREAK primitives). Instead, persistent connections may be removable by a link reset. Persistent connections may be used in situations in which the overhead associated with the usual tear down and re-establishment of connections in a SAS network may be considered too high in comparison with its intended benefits. Persistent connections may also be used to provide virtual direct attachment between two different SAS connected devices or between a SAS connected device and an expander.
摘要:
Given the different configurations for SAS and SATA Host and Target Ports, embodiments of the present invention automatically detect the configuration of SATA and SAS Phys when any device is inserted into a port enclosure and properly configure the connection regardless of the Phy configuration of the connected device. When a device is connected to the system, the port listens for either a SATA or SAS OOB signal to determine if the receive pin of the port is properly connected to the transmit signal of the attached device. By switching the configuration periodically and listening for the OOB signal, the port can determine which configuration is proper. Once a signal is detected, the port can properly configure the connection and continue with the SATA or SAS insertion algorithm. A user may alternatively choose which configuration to use and bypass the automatic detection and configuration.
摘要:
When a new device is attached to a SAS expander, malfunctioning devices can cause many BCNs to be generated, which in turn can cause excessive re-discovery processes to be performed by initiators in a storage network. Therefore, the isolation of devices from the storage network until they can be validated as healthy is disclosed. Any device malfunctions during this time of isolation do not cause BCNs to be generated and do not cause re-discovery processes to be performed. Once the device is validated (via a port-test-before-insertion approach) and found to be healthy, the fabric is notified via a BCN, and the device can be made visible to the network.
摘要:
The automatic mapping of a set of physical drives to virtual drives is disclosed. Given a maximum set of n physical servers, S1-Sn, and a maximum set of m physical drives, D1-Dm, a mapping of a set of virtual drives, V1-Vn, to the physical drives D1-Dm, is created, assuming n and m are fixed and known, and one virtual drive is created per server. Physical drives of size Dsize are organized into a maximum of p “Stripe Sets” SS1-SSp, each Stripe Set containing an equal number of physical drives. Each virtual drive will have a size, Vsize=(m*Dsize)/n (rounded down to the nearest integer). Virtual drives are mapped sequentially to Stripe Sets, starting with V1 mapped to SS1. Successive virtual drives are mapped to Stripe Sets until all virtual drives have been mapped to a Stripe Set.
摘要:
A switch connection lock and release mechanism is disclosed to prevent out-of-order frames from being received by FC and/or SATA devices. The mechanism includes a set of previous AL_PA registers, alpa_reg[N: 0], one for each port, and a bit vector, prev_conn[M:0], one bit for each Buffer Bank (BB). If a connection is closed prematurely, the valid AL_PA of the destination device and the source port number are stored in the previous AL_PA register associated with the destination port, and the bit in the bit vector associated with the source BB is asserted. Together, the valid AL_PA, the source port and the asserted bit form a connection lock on the destination port that effectively will deny access to the destination port to all BBs with the same destination AL_PA and source port number except the source BB.