ACTIVE FUNCTIONAL LIMITING OF A MICROCONTROLLER
    51.
    发明申请
    ACTIVE FUNCTIONAL LIMITING OF A MICROCONTROLLER 有权
    微控制器的主动功能限制

    公开(公告)号:US20130332046A1

    公开(公告)日:2013-12-12

    申请号:US13914264

    申请日:2013-06-10

    IPC分类号: G06F1/06

    摘要: A microcontroller for use in a control device for an internal combustion engine includes: an analysis access via which internal data in the microcontroller can be accessed from outside the microcontroller; a clock generator which generates clock timing for data communication of the microcontroller with other units. The microcontroller is configured to change over from a first clock to a second clock when there is an access to the microcontroller via the analysis access.

    摘要翻译: 用于内燃机的控制装置的微控制器包括:分析存取器,通过该分析存取器可以从微控制器外部访问微控制器中的内部数据; 时钟发生器,其产生用于与其他单元的微控制器的数据通信的时钟定时。 微控制器配置为通过分析访问访问微控制器时,从第一个时钟切换到第二个时钟。

    Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto
    52.
    发明授权
    Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto 有权
    包括第一半导体芯片和与其连接的第二半导体芯片的布置

    公开(公告)号:US08380899B2

    公开(公告)日:2013-02-19

    申请号:US13355130

    申请日:2012-01-20

    IPC分类号: G06F13/12 G06F13/38

    摘要: A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.

    摘要翻译: 一种用于半导体芯片的数据通信方法,包括从第一半导体芯片向一个或多个第二半导体芯片发送负载控制数据,导频数据和传输时钟信号,所述第二半导体芯片分别耦合到一个或多个电负载,基于 由负载控制数据定义的定时,通过将传输时钟信号除以由导频数据规定的分频因子得出传输速率,并以传输速率从一个或多个第二半导体芯片向第一半导体芯片发送诊断数据。

    TIMING MODULE
    53.
    发明申请
    TIMING MODULE 审中-公开
    时序模块

    公开(公告)号:US20120079239A1

    公开(公告)日:2012-03-29

    申请号:US13213773

    申请日:2011-08-19

    IPC分类号: G06F15/78 G06F9/02

    CPC分类号: G06F1/04 G06F1/10

    摘要: A timing module and a microcontroller. An independent processing unit, which is provided as a component of at least one closed-loop control circuit, is integrated in the timing module.

    摘要翻译: 定时模块和微控制器。 作为至少一个闭环控制电路的组件提供的独立处理单元集成在定时模块中。

    Method for testing at least one arithmetic unit installed in a control unit
    54.
    发明授权
    Method for testing at least one arithmetic unit installed in a control unit 有权
    用于测试安装在控制单元中的至少一个运算单元的方法

    公开(公告)号:US07913142B2

    公开(公告)日:2011-03-22

    申请号:US12224735

    申请日:2007-02-26

    申请人: Axel Aue

    发明人: Axel Aue

    IPC分类号: G01R31/28

    CPC分类号: G06F11/2236

    摘要: A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.

    摘要翻译: 一种用于测试安装在控制单元中的至少两个运算单元的方法包括:加载用于测试第一运算单元的第一测试数据; 将加载的第一测试数据保存在第二运算单元的第二存储器单元中; 将所述第一算术单元切换到可访问所述第一算术单元的第一扫描链的测试模式; 从第二存储器单元读取第一测试数据; 将通过第一运算单元的第一扫描链读取的第一测试数据移动到用于提供第一运算单元的测试结果数据的测试模式; 检查提供的测试结果数据以获得为第一运算单元提供测试结果的合理性。

    Method for transmitting data from and to a control device
    55.
    发明授权
    Method for transmitting data from and to a control device 有权
    用于从控制装置发送数据的方法

    公开(公告)号:US07882298B2

    公开(公告)日:2011-02-01

    申请号:US12226703

    申请日:2007-04-19

    申请人: Axel Aue

    发明人: Axel Aue

    IPC分类号: G06F13/00

    摘要: A method for transmitting data from and to a control device, in particular an engine control device for a motor vehicle that has a first communication interface and a second communication interface , the method having the following steps: connecting the first communication interface to a development tool, and connecting the second communication interface to one or more function units during the development phase of the control device, transmitting data from the control device to the development tool via the first communication interface using a first communication protocol, transmitting data from the development tool to the control device via the first communication interface using the first communication protocol, breaking the connection between the first communication interface and the development tool, connecting the first communication interface to one or more additional 20 function units, and transmitting data between the control device and the other function unit or function units via the first communication interface using a second communication protocol.

    摘要翻译: 一种用于从控制装置,特别是具有第一通信接口和第二通信接口的机动车辆的发动机控制装置发送数据的方法,该方法具有以下步骤:将第一通信接口连接到开发工具 并且在所述控制装置的开发阶段将所述第二通信接口连接到一个或多个功能单元,使用第一通信协议经由所述第一通信接口从所述控制装置向所述开发工具发送数据,将数据从所述开发工具传送到 所述控制装置经由所述第一通信接口使用所述第一通信协议,破坏所述第一通信接口和所述开发工具之间的连接,将所述第一通信接口连接到一个或多个附加的20个功能单元,以及在所述控制设备和所述控制设备之间传送数据 其他功能单元或功能单元 通过第一通信接口使用第二通信协议。

    METHOD OF DETECTING MANIPULATION OF A PROGRAMMABLE MEMORY DEVICE OF A DIGITAL CONTROLLER
    56.
    发明申请
    METHOD OF DETECTING MANIPULATION OF A PROGRAMMABLE MEMORY DEVICE OF A DIGITAL CONTROLLER 有权
    检测数字控制器的可编程存储器件的操作方法

    公开(公告)号:US20090187305A1

    公开(公告)日:2009-07-23

    申请号:US12414404

    申请日:2009-03-30

    IPC分类号: G06F19/00

    摘要: A method of detecting manipulation of a programable memory device of a digital controller for a motor vehicle is described; data and control programs for operation of the controller and for control/regulation of certain functions of the motor vehicle can be stored in the memory device. To permit especially reliable detection of manipulation in the simplest possible way, in conjunction with each programing/reprograming operation of the programable memory device, information regarding the programing/reprograming operation is stored in a separate memory area of the memory device where only reading and programing are possible, and in order to detect manipulation, the content of the separate memory area is read out and compared with given information.

    摘要翻译: 描述了一种检测用于机动车辆的数字控制器的可编程存储器件的操作的方法; 用于控制器的操作和用于控制/调节机动车辆的某些功能的数据和控制程序可以存储在存储装置中。 为了以最简单可能的方式特别可靠地检测操作,结合可编程存储器件的每个编程/重新编程操作,关于编程/重新编程操作的信息被存储在存储器件的单独存储器区域中,其中仅读取和编程 为了检测操作,读出分离的存储区域的内容并与给定的信息进行比较。

    METHOD FOR RECOGNIZING A POWER FAILURE IN A DATA MEMORY AND RECOVERING THE DATA MEMORY
    57.
    发明申请
    METHOD FOR RECOGNIZING A POWER FAILURE IN A DATA MEMORY AND RECOVERING THE DATA MEMORY 有权
    用于识别数据存储器中的电源故障并恢复数据存储器的方法

    公开(公告)号:US20090158089A1

    公开(公告)日:2009-06-18

    申请号:US12097324

    申请日:2006-12-12

    申请人: Axel Aue

    发明人: Axel Aue

    IPC分类号: G06F11/07

    摘要: To detect a power failure in a volatile data memory containing useful data units and test data units associated with the useful data units, the associated test data unit is also read when the useful data unit is read-accessed, and a decision is made as to whether the useful data unit is corrupted based on the test data unit. A power failure is identified when at least two read useful data units within a predefined number of successive read accesses are found to be corrupted.

    摘要翻译: 为了检测包含有用数据单元和与有用数据单元相关联的测试数据单元的易失性数据存储器中的电源故障,当有用数据单元被读取访问时,还读取相关联的测试数据单元,并且作出关于 基于测试数据单元是否损坏了有用的数据单元。 当发现预定数量的连续读访问中的至少两个读有用数据单元被破坏时,识别出电源故障。

    Method for protecting a microcomputer system against manipulation of data stored in a storage arrangement of the microcomputer system
    58.
    发明授权
    Method for protecting a microcomputer system against manipulation of data stored in a storage arrangement of the microcomputer system 失效
    用于保护微型计算机系统免受操纵存储在微计算机系统的存储装置中的数据的方法

    公开(公告)号:US07207066B2

    公开(公告)日:2007-04-17

    申请号:US09766102

    申请日:2001-01-19

    IPC分类号: G06F12/14 H04L9/32

    CPC分类号: G06F21/78

    摘要: A method for protecting a microcomputer system against manipulation of data stored in a storage arrangement of the microcomputer system, in particular for protecting a program stored in the storage arrangement. The microcomputer system includes a microcomputer assigned to the storage arrangement, the microcomputer accessing the storage arrangement for the purpose of processing the data, i.e., the program. In order to prevent the manipulation of data in a microcomputer that does not have an internal memory but rather accesses an external storage arrangement and processes the stored data, it is proposed that before the storage arrangement is accessed, an individual identifier be assigned to the or to each allocated microcomputer or to the storage arrangement that a comparison code be generated as a function of the individual identifier and be stored in the storage arrangement, and that, before or during the operation of the microcomputer system, a security code be generated as a function of the individual identifier and be compared with the comparison code.

    摘要翻译: 一种用于保护微型计算机系统免受操纵存储在微计算机系统的存储装置中的数据的方法,特别是用于保护存储在存储装置中的程序。 微型计算机系统包括分配给存储装置的微型计算机,为了处理数据即程序而访问存储装置的微型计算机。 为了防止在不具有内部存储器的微型计算机中的数据的操作,而是访问外部存储装置并处理存储的数据,建议在存储装置被访问之前,将个体标识符分配给或 到每个分配的微型计算机或存储装置,作为个人标识符的函数产生比较代码并存储在存储装置中,并且在微计算机系统的操作之前或期间,生成安全码作为 功能,并与比较代码进行比较。

    Device for linking a processor to a memory element and memory element
    59.
    发明授权
    Device for linking a processor to a memory element and memory element 失效
    用于将处理器链接到存储器元件和存储器元件的装置

    公开(公告)号:US06774677B2

    公开(公告)日:2004-08-10

    申请号:US10252946

    申请日:2002-09-23

    申请人: Axel Aue

    发明人: Axel Aue

    IPC分类号: H03K190175

    CPC分类号: G11C7/1006 G11C8/00

    摘要: A device having a processor and a memory element positioned outside the processor, as well as a device for linking a memory element to a processor, and a memory element, are described, the processor and the memory element being linked via address and/or data lines, the address and/or data lines each being implemented in a structure combining a differential structure, LVDS in particular, and a structure having transistors which switch to ground and voltage, SSTL in particular, which has corresponding transmitters and receivers.

    摘要翻译: 描述了具有位于处理器外部的处理器和存储元件的设备以及用于将存储器元件链接到处理器和存储器元件的设备,处理器和存储器元件通过地址和/或数据链接 线路,地址和/或数据线各自以组合差分结构,特别是LVDS的结构和具有切换到接地和电压的晶体管,特别是具有对应的发射器和接收器的SSTL的结构来实现的结构。

    Arrangement and method for signal processing and storing
    60.
    发明授权
    Arrangement and method for signal processing and storing 失效
    信号处理和存储的布置和方法

    公开(公告)号:US06728796B2

    公开(公告)日:2004-04-27

    申请号:US09769700

    申请日:2001-01-25

    申请人: Axel Aue Dirk Martin

    发明人: Axel Aue Dirk Martin

    IPC分类号: G06F930

    摘要: A method is described for storing and processing/filtering signals, as well as a memory arrangement, a signal processing arrangement and, in particular, a digital filter arrangement having a plurality of filter modules for digital processing/filtering of input values, having a memory area and a signal processing module, which contains in particular at least one multiplier-accumulator which has at least one multiplier and at least one adder. The input values, coefficients, and output values of the arrangement can be stored in the memory area and called up again therefrom as needed. The input values are gated with the coefficients to form output values. In order to alleviate the load on a higher-level microprocessor by digital processing/filtering of the input values, it is proposed that the digital filter arrangement have a Direct Memory Access controller for coordinating data transmission of the filter coefficients, input values and output values between the multiplier-accumulator and the memory area.

    摘要翻译: 描述了一种用于存储和处理/滤波信号的方法,以及存储器布置,信号处理装置,特别是具有多个用于输入值的数字处理/滤波的滤波器模块的数字滤波器装置,具有存储器 区域和信号处理模块,其特别地包含至少一个具有至少一个乘法器和至少一个加法器的乘法器累加器。 该布置的输入值,系数和输出值可以存储在存储器区域中,并且根据需要再次被调出。 输入值与系数门控以形成输出值。 为了通过对输入值的数字处理/滤波来减轻对较高级微处理器的负担,提出了数字滤波器装置具有用于协调滤波器系数的数据传输的直接存储器访问控制器,输入值和输出值 在乘法器累加器和存储器区域之间。