Method and device for testing a computer core in a processor having at least two computer cores

    公开(公告)号:US09740584B2

    公开(公告)日:2017-08-22

    申请号:US13124445

    申请日:2009-09-03

    IPC分类号: G06F11/22

    CPC分类号: G06F11/2236

    摘要: A method and a device for testing a computer core in a processor having at least two computer cores is described. The computer cores are connected to each other via an internal connecting system, both computer cores contributing toward the operating sequence of a machine. In the method for testing a computer core, with which a high error detection rate may be achieved in a minimum outlay of time, a test is run in one computer core, while a program for executing the driving operation of the motor vehicle is being processed in the other computer core at the same time.

    Active functional limiting of a microcontroller
    2.
    发明授权
    Active functional limiting of a microcontroller 有权
    微控制器的主动功能限制

    公开(公告)号:US09176523B2

    公开(公告)日:2015-11-03

    申请号:US13914264

    申请日:2013-06-10

    摘要: A microcontroller for use in a control device for an internal combustion engine includes: an analysis access via which internal data in the microcontroller can be accessed from outside the microcontroller; a clock generator which generates clock timing for data communication of the microcontroller with other units. The microcontroller is configured to change over from a first clock to a second clock when there is an access to the microcontroller via the analysis access.

    摘要翻译: 用于内燃机的控制装置的微控制器包括:分析存取器,通过该分析存取器可以从微控制器外部访问微控制器中的内部数据; 时钟发生器,其产生用于与其他单元的微控制器的数据通信的时钟定时。 微控制器配置为通过分析访问访问微控制器时,从第一个时钟切换到第二个时钟。

    Method for Transmitting Data From and to a Control Device
    4.
    发明申请
    Method for Transmitting Data From and to a Control Device 有权
    从控制设备传输数据的方法

    公开(公告)号:US20090083463A1

    公开(公告)日:2009-03-26

    申请号:US12226703

    申请日:2007-04-19

    申请人: Axel Aue

    发明人: Axel Aue

    IPC分类号: G06F13/42 F02D45/00

    摘要: A method for transmitting data from and to a control device, in particular an engine control device for a motor vehicle that has a first communication interface and a second communication interface, the method having the following steps: connecting the first communication interface to a development tool, and connecting the second communication interface to one or more function units during the development phase of the control device, transmitting data from the control device to the development tool via the first communication interface using a first communication protocol, transmitting data from the development tool to the control device via the first communication interface using the first communication protocol, breaking the connection between the first communication interface and the development tool, connecting the first communication interface to one or more additional 20 function units, and transmitting data between the control device and the other function unit or function units via the first communication interface using a second communication protocol.

    摘要翻译: 一种用于从控制装置,特别是具有第一通信接口和第二通信接口的机动车辆的发动机控制装置发送数据的方法,该方法具有以下步骤:将第一通信接口连接到开发工具 并且在所述控制装置的开发阶段将所述第二通信接口连接到一个或多个功能单元,使用第一通信协议经由所述第一通信接口从所述控制装置向所述开发工具发送数据,将数据从所述开发工具传送到 所述控制装置经由所述第一通信接口使用所述第一通信协议,破坏所述第一通信接口和所述开发工具之间的连接,将所述第一通信接口连接到一个或多个附加的20个功能单元,以及在所述控制设备和所述控制设备之间传送数据 其他功能单元或功能单元 经由第一通信接口使用第二通信协议。

    Method for reliably verifying a memory area of a microcontroller in a control unit and control unit having a protected microcontroller
    5.
    发明授权
    Method for reliably verifying a memory area of a microcontroller in a control unit and control unit having a protected microcontroller 有权
    用于可靠地验证控制单元中的微控制器的存储区域和具有被保护的微控制器的控制单元的方法

    公开(公告)号:US07293148B2

    公开(公告)日:2007-11-06

    申请号:US10534372

    申请日:2003-11-05

    IPC分类号: G06F12/14

    CPC分类号: G06F21/71

    摘要: A method is provided for controlling a microcontroller in a control unit in a motor vehicle, having a processor core, at least one read-only memory area and at least one rewritable memory area, at least one control program which is intended to be processed by the processor core being stored in the rewritable memory area. In order to provide a method for controlling a microcontroller in a control unit that better protects the verification of memories of the microcontroller against unauthorized intervention, a verification program is stored in a write-once memory area of the rewritable memory area and a service program is stored in the read-only memory area. The verification program is called by the control program via the service program at regular intervals and verifies at least part of the rewritable memory area. In addition, the service program resets a counter. A RESET of the control unit is triggered by the verification program when manipulation of the verified memory area is detected or by the counter in the event of counter overflow.

    摘要翻译: 提供了一种用于控制机动车辆中的控制单元中的微控制器的方法,其具有处理器核心,至少一个只读存储器区域和至少一个可重写存储器区域,至少一个控制程序旨在由 处理器核心存储在可重写存储器区域中。 为了提供一种用于控制控制单元中的微控制器的方法,其更好地保护对微控制器的存储器的验证以防未经授权的干预,将验证程序存储在可重写存储器区域的一次写入存储器区域中,并且服务程序为 存储在只读存储器区域中。 验证程序由控制程序经由服务程序以规则的间隔调用,并验证至少部分可重写存储器区域。 另外,服务程序重置一个计数器。 当检测到验证的存储区域的操作时,由验证程序触发控制单元的复位,或者在计数器溢出的情况下由计数器触发控制单元的复位。

    Method and device for monitoring an electronic circuit
    6.
    发明申请
    Method and device for monitoring an electronic circuit 有权
    用于监控电子电路的方法和装置

    公开(公告)号:US20070033492A1

    公开(公告)日:2007-02-08

    申请号:US10544560

    申请日:2004-02-09

    申请人: Jochen Weber Axel Aue

    发明人: Jochen Weber Axel Aue

    IPC分类号: G11C29/00

    摘要: A method and apparatus for monitoring an electronic control system such that provision is made for the complete data of at least one memory to be read sequentially into an ECC unit, which can be filled very rapidly from the memory, and automatically checked there, with no need to transfer the complete data in time-consuming fashion to a processor; the ECC check width encompassing the data of a plurality of memory cells of the memory and being able to be a multiple of the read word width of the processor; an additional datum being created in each case for the data of a ECC check width and being storable in the memory, and the entire code/data region of the at least one memory therefore being able to be checked, outside the ongoing instruction accesses, by the fact that for each request by the processor for the contents of a single memory cell, the ECC unit is filled from the memory to the entire ECC check width including the additional datum; a check datum being created from the data of the complete ECC check width and the check datum automatically being compared, in the ECC unit, with the stored additional datum.

    摘要翻译: 一种用于监控电子控制系统的方法和装置,使得为了将要被顺序读取的至少一个存储器的完整数据提供给ECC单元,该ECC单元可以从存储器中非常快速地填充并且在那里自动检查,没有 需要将完整的数据以耗时的方式传输到处理器; 所述ECC检查宽度包含所述存储器的多个存储器单元的数据,并且能够是所述处理器的读取字宽度的倍数; 在每种情况下创建用于ECC检查宽度的数据并且可存储在存储器中的附加数据,并且所述至少一个存储器的整个代码/数据区域能够在正在进行的指令访问之外通过 事实是,对于处理器对于单个存储器单元的内容的每个请求,将ECC单元从存储器填充到包括附加数据的整个ECC检查宽度; 根据完整的ECC检查宽度的数据和在ECC单元中自动比较检查数据的检查数据与存储的附加数据一起创建。

    Arrangement for voltage supply to a volatile semiconductor memory
    7.
    发明授权
    Arrangement for voltage supply to a volatile semiconductor memory 失效
    用于向易失性半导体存储器供电的布置

    公开(公告)号:US06816428B2

    公开(公告)日:2004-11-09

    申请号:US10169446

    申请日:2002-11-12

    IPC分类号: G11C700

    摘要: A system for supplying power to a volatile semiconductor memory having a memory array, with the semiconductor memory being provided with a standby voltage that is present at a second connection of the semiconductor memory. To implement the power supply system as simply and with as few components as possible, the semiconductor memory is provided with a stabilization circuit for stabilizing the standby voltage that has a low impedance when the input voltage is elevated and a high impedance when the input voltage is too low to supply the semiconductor memory.

    摘要翻译: 一种用于向具有存储器阵列的易失性半导体存储器供电的系统,其中半导体存储器具有存在于半导体存储器的第二连接处的备用电压。 为了简单且尽可能少的部件实现电源系统,半导体存储器设置有稳定电路,用于稳定当输入电压升高时具有低阻抗的待机电压,并且当输入电压为 太低,无法提供半导体存储器。

    Method and device for refreshing the memory content of a memory cell of a read-only memory
    8.
    发明授权
    Method and device for refreshing the memory content of a memory cell of a read-only memory 失效
    用于刷新只读存储器的存储器单元的存储器内容的方法和装置

    公开(公告)号:US06438056B2

    公开(公告)日:2002-08-20

    申请号:US09750666

    申请日:2000-12-29

    申请人: Axel Aue

    发明人: Axel Aue

    IPC分类号: G11C800

    CPC分类号: G11C16/3431 G11C16/3418

    摘要: A method and a device for refreshing the memory content of at least one memory cell of a read-only memory is described. An embodiment of the present invention involves determining the instantaneous charge status of the memory cell; comparing the instantaneous charge status of the memory cell with a charge threshold (U_schw) which is greater than the reading charge (U_erh) sufficient for correct detection of the memory content of the memory cell; and raising the charge status of the memory cell if the instantaneous charge status of the memory cell is below the charge threshold (U_schw).

    摘要翻译: 描述用于刷新只读存储器的至少一个存储器单元的存储器内容的方法和设备。 本发明的实施例涉及确定存储器单元的瞬时充电状态; 将存储器单元的瞬时充电状态与大于读取电荷(U_erh)的充电阈值(U_schw)进行比较,以充分检测存储器单元的存储器内容; 如果存储器单元的瞬时充电状态低于充电阈值(U_schw),则提高存储单元的充电状态。

    Control unit including a computing device and a peripheral module which are interconnected via a serial multiwire bus
    9.
    发明授权
    Control unit including a computing device and a peripheral module which are interconnected via a serial multiwire bus 有权
    控制单元包括通过串行多线总线互连的计算设备和外围模块

    公开(公告)号:US08713225B2

    公开(公告)日:2014-04-29

    申请号:US11991774

    申请日:2006-09-01

    IPC分类号: G06F13/38

    CPC分类号: G06F13/4072

    摘要: A control unit includes at least one computing device and at least one separate peripheral module which is connected to the computing device via a serial multiwire bus, the peripheral module including at least one output stage for transferring serial data to means outside of the control unit. In order to keep the number of pins required on a peripheral module to a minimum, thereby reducing costs for the entire control unit, the peripheral module has an asynchronous single-wire interface between one interface for the serial multiwire bus and the output stage. The asynchronous single-wire interface is preferably a UART (universal asynchronous receiver/transmitter) interface. The serial multiwire bus is preferably a microsecond bus.

    摘要翻译: 控制单元包括至少一个计算设备和经由串行多线总线连接到计算设备的至少一个单独的外围模块,所述外围模块包括用于将串行数据传送到控制单元之外的装置的至少一个输出级。 为了将外围模块所需的引脚数保持在最低限度,从而降低整个控制单元的成本,外围模块在串行多线总线的一个接口和输出级之间具有异步单线接口。 异步单线接口最好是一个UART(通用异步收发器)接口。 串行多线总线优选为微秒总线。

    ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMICONDUCTOR CHIP CONNECTED THERETO
    10.
    发明申请
    ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMICONDUCTOR CHIP CONNECTED THERETO 有权
    包含第一半导体芯片和连接的第二个半导体芯片的布置

    公开(公告)号:US20120117283A1

    公开(公告)日:2012-05-10

    申请号:US13355130

    申请日:2012-01-20

    IPC分类号: G06F3/00

    摘要: A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.

    摘要翻译: 一种用于半导体芯片的数据通信方法,包括从第一半导体芯片向一个或多个第二半导体芯片发送负载控制数据,导频数据和传输时钟信号,所述第二半导体芯片分别耦合到一个或多个电负载,基于 由负载控制数据定义的定时,通过将传输时钟信号除以由导频数据规定的分频因子得出传输速率,并以传输速率从一个或多个第二半导体芯片向第一半导体芯片发送诊断数据。