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    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms
    51.
    发明授权
    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms 失效
    拆分套接字发送队列设备和方法，具有高效的队列流控制，重传和备份支持机制

    公开(公告)号：US07818362B2

    公开(公告)日：2010-10-19

    申请号：US11418606

    申请日：2006-05-05

    Applicant: William Todd Boyd ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Douglas J. Joseph ,  Renato John Recio

    Inventor： William Todd Boyd ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Douglas J. Joseph ,  Renato John Recio

    IPC: G06F15/16 ,  G06F3/00

    CPC classification number: H04L47/10 ,  H04L47/193 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162

    Abstract: A mechanism for offloading the management of send queues in a split socket stack environment, including efficient split socket queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates send work queue entries (SWQEs) for writing to the send work queue (SWQ). The Internet Protocol Suite Offload Engine (IPSOE) is notified of a new entry to the SWQ and it subsequently reads this entry that contains pointers to the data that is to be transmitted. After the data is transmitted and acknowledgments are received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). The flow control between the ULP and the IPSOE is credit based. The passing of CQ credits is the only explicit mechanism required to manage flow control of both the SWQ and the CQ between the ULP and the IPSOE.

    Abstract translation: 一种卸载分组套接字堆栈环境中发送队列管理的机制，包括高效的分裂套接字队列流控制和TCP / IP重传支持。 上层协议（ULP）创建用于写入发送工作队列（SWQ）的发送工作队列条目（SWQE）。 Internet协议套件卸载引擎（IPSOE）被通知一个新的条目到SWQ，它随后读取这个条目，其中包含指向要发送的数据的指针。 在发送数据并接收到确认之后，IPSOE创建写入完成队列（CQ）的完成队列条目（CQE）。 ULP和IPSOE之间的流量控制是基于信用的。 CQ信用证的通过是在ULP和IPSOE之间管理SWQ和CQ两者流量控制所需的唯一明确的机制。

    Systems and methods for multi-frame control blocks
    54.
    发明授权
    Systems and methods for multi-frame control blocks 有权
    多帧控制块的系统和方法

    公开(公告)号：US07603539B2

    公开(公告)日：2009-10-13

    申请号：US12039304

    申请日：2008-02-28

    Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

    Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

    IPC: G06F12/00

    CPC classification number: H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

    Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

    Abstract translation: 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

    FLEXIBLE NETWORK PROCESSOR SCHEDULER AND DATA FLOW
    55.
    发明申请
    FLEXIBLE NETWORK PROCESSOR SCHEDULER AND DATA FLOW 失效
    灵活的网络处理器调度器和数据流

    公开(公告)号：US20090175275A1

    公开(公告)日：2009-07-09

    申请号：US12348938

    申请日：2009-01-06

    Applicant: Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

    Inventor： Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

    IPC: H04L12/56

    CPC classification number: H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

    Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

    Abstract translation: 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

    Apparatus and method for efficiently modifying network data frames
    56.
    发明授权
    Apparatus and method for efficiently modifying network data frames 失效
    用于有效修改网络数据帧的装置和方法

    公开(公告)号：US07522621B2

    公开(公告)日：2009-04-21

    申请号：US11030344

    申请日：2005-01-06

    Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Fabrice J. Verplanken

    Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Fabrice J. Verplanken

    IPC: H04L12/56

    CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9021

    Abstract: Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.

    Abstract translation: 用于存储要修改的网络帧数据的装置和方法。 多个缓冲器存储布置在由帧控制块和缓冲器控制块所标识的数据结构中的网络数据。 与存储帧数据的每个缓冲器相关联的多个缓冲器控制块建立缓冲器的序列。 每个缓冲器控制块具有用于识别序列内的后续缓冲器的数据。 第一缓冲器由帧控制块的字段以及帧数据的开始和结束地址来标识。 可以通过改变缓冲器控制块和/或帧控制块内容而不将数据重写到存储器来修改帧数据，而不必复制或重写数据以便修改它。

    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms
    57.
    发明授权
    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms 失效
    拆分套接字发送队列设备和方法，具有高效的队列流控制，重传和备份支持机制

    公开(公告)号：US07519650B2

    公开(公告)日：2009-04-14

    申请号：US10235689

    申请日：2002-09-05

    Applicant: William Todd Boyd ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Douglas J. Joseph ,  Renato John Recio

    Inventor： William Todd Boyd ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Douglas J. Joseph ,  Renato John Recio

    IPC: G06F15/16

    CPC classification number: H04L47/10 ,  H04L47/193 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162

    Abstract: A mechanism for offloading the management of send queues in a split socket stack environment, including efficient split socket queue flow control and TCP/IP retransmission support. As consumers initiate send operations, send work queue entries (SWQEs) are created by an Upper Layer Protocol (ULP) and written to the send work queue (SWQ). The Internet Protocol Suite Offload Engine (IPSOE) is notified of a new entry to the SWQ and it subsequently reads this entry that contains pointers to the data that is to be transmitted. After the data is transmitted and acknowledgments are received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the SWQ and CQ. The number of entries available in the SWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ. The flow control between the ULP and the IPSOE is credit based. The passing of CQ credits is the only explicit mechanism required to manage flow control of both the SWQ and the CQ between the ULP and the IPSOE.

    Abstract translation: 一种卸载分组套接字堆栈环境中发送队列管理的机制，包括高效的分裂套接字队列流控制和TCP / IP重传支持。 当消费者发起发送操作时，发送工作队列条目（SWQE）由上层协议（ULP）创建并写入发送工作队列（SWQ）。 互联网协议套件卸载引擎（IPSOE）被通知一个新条目到SWQ，它随后读取这个条目，其中包含指向要发送的数据的指针。 在发送数据并接收到确认之后，IPSOE创建写入完成队列（CQ）的完成队列条目（CQE）。 在编写CQE后，ULP随后处理该条目并将其从CQE中删除，从而释放了SWQ和CQ两者的空间。 SWQ中可用的条目数由ULP进行监视，以使其不会覆盖任何有效的条目。 同样，IPSOE监视CQ中可用条目的数量，以免覆盖CQ。 ULP和IPSOE之间的流量控制是基于信用的。 CQ信用证的通过是在ULP和IPSOE之间管理SWQ和CQ两者流量控制所需的唯一明确的机制。

    STRUCTURE AND METHOD FOR SCHEDULER PIPELINE DESIGN FOR HIERARCHICAL LINK SHARING
    59.
    发明申请
    STRUCTURE AND METHOD FOR SCHEDULER PIPELINE DESIGN FOR HIERARCHICAL LINK SHARING 失效
    用于分层链路共享的调度器管道设计的结构和方法

    公开(公告)号：US20080298372A1

    公开(公告)日：2008-12-04

    申请号：US12175479

    申请日：2008-07-18

    Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    IPC: H04L12/56

    CPC classification number: H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

    Abstract: A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

    Abstract translation: 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

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