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公开(公告)号：US20210250503A1
公开(公告)日：2021-08-12
申请号：US16784257
申请日：2020-02-07
发明人： Chih-Yen Yang , Yu-Yu Sung
摘要： A multi-mode image sensor applicable to image sensing and additional detection is provided. The multi-mode image sensor includes: a photodiode array, a hybrid type color filter array that is positioned on the photodiode array, and a mode controller. The photodiode array may include a plurality of photodiodes. The hybrid type color filter array may be arranged to perform optical filtering for the photodiode array. The mode controller may activate the photodiode array to output corresponding photo detection results in any of at least two modes. For example, in addition to an image sensing mode, the at least two modes may further include an ambient light sensor (ALS) mode and/or a proximity sensor (PS) mode.
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公开(公告)号：US11063598B1
公开(公告)日：2021-07-13
申请号：US17072671
申请日：2020-10-16
发明人： Xufeng Bao , Hack Soo Oh , Youngchul Sohn , Amit Mittra
摘要： A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates a PLL output signal having an oscillation frequency controlled by a control signal; a phase detector that generates a phase signal representing a difference in phase between the PLL output signal and a reference signal; a loop filter coupled to receive the phase signal; a switch; and a sampling circuit switchably coupled to receive the control signal of the VCO via the switch, and generating a code representing the control signal.
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公开(公告)号：US20210006742A1
公开(公告)日：2021-01-07
申请号：US16504321
申请日：2019-07-07
发明人： Hack soo Oh , Amit Mittra
IPC分类号： H04N5/376 , H04N5/3745 , H04N5/378 , H04N5/353
摘要： An image sensor is provided, wherein the image sensor includes a pixel array and a timing controller coupled to the pixel array. The pixel array includes a plurality of pixel circuits, and each pixel circuit of pixel circuits includes a photodiode and a storage node. The timing controller includes a logic circuit for generating a plurality of control signals to respectively control operations of the pixel circuits within the pixel array. Respective photodiodes of the pixel circuits are concurrently reset to a first reference level before generating respective photodiode signals of the pixel circuits. Respective storage nodes of the pixel circuits are sequentially reset to a second reference level. The respective photodiode signals of the pixel circuits are concurrently transmitted to the respective storage nodes of the pixel circuits. The respective photodiode signals of the pixel circuits are sequentially read out from the respective storage nodes of the pixel circuits.
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公开(公告)号：US20200288080A1
公开(公告)日：2020-09-10
申请号：US16884078
申请日：2020-05-27
发明人： Hack soo Oh , Yu Hin Desmond Cheung , Kihong Kim
IPC分类号： H04N5/3745 , H04N5/378
摘要： A pixel circuit includes a front-end circuit, a signal storage circuit, and an output circuit. All of the front-end circuit, the signal storage circuit and the output circuit are coupled to a common floating diffusion (FD) node. The front-end circuit is arranged to generate pixel signals. The signal storage circuit is arranged to store the pixel signals generated by the front-end circuit, wherein when the pixel circuit is selected for performing a read-out operation, the pixel signals stored in the signal storage circuit are pulled up from original voltage levels to other voltage levels higher than the original voltage levels according to a voltage increment applied to a control voltage of the signal storage circuit. When the pixel circuit is selected for performing the read-out operation, the output circuit generates output signals on an output terminal according to voltage levels of the common FD node, respectively.
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公开(公告)号：US10771725B1
公开(公告)日：2020-09-08
申请号：US16503435
申请日：2019-07-03
发明人： Hack soo Oh
IPC分类号： H04N5/355 , H04N5/374 , H04N5/378 , H04N5/3745
摘要： A pixel circuit is provided, where the pixel circuit comprises a photodiode, a buffer circuit, a first capacitor, a first switch, a second switch and a third switch. The photodiode is configured to accumulate charges in response to incident radiation, to generate a photodiode signal. The buffer circuit is configured to output at least one read-out signal, wherein an input terminal of the buffer circuit is coupled to a specific node. The first capacitor is coupled between a control voltage terminal of the pixel circuit and the specific node. The first switch is coupled between the photodiode and the specific node. The second switch is coupled between the input terminal of the buffer circuit and an output terminal of the buffer circuit. The third switch is coupled between the output terminal of the buffer circuit and a read-out terminal of the pixel circuit.
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公开(公告)号：US20200267302A1
公开(公告)日：2020-08-20
申请号：US16280061
申请日：2019-02-20
发明人： Amit MITTRA , Tony CHIANG
摘要： A camera system is provided and includes a processor, a first camera, a second camera, and a data bus. The processor transmits a first trigger signal to the first camera to enable the first camera outputting first data to the processor through the data bus. The first camera transmits a second trigger signal to the second camera to enable the second camera outputting second data to the processor through the data bus.
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公开(公告)号：US20200077040A1
公开(公告)日：2020-03-05
申请号：US16181345
申请日：2018-11-06
发明人： Hack soo Oh , Yu Hin Desmond Cheung , Kihong Kim
IPC分类号： H04N5/3745 , H04N5/378
摘要： A pixel circuit is disclosed. The pixel circuit includes a photodiode (PD), a transmission circuit, a reset circuit, a signal storage circuit and a buffer circuit. The transmission circuit is coupled between the PD and an ordinary floating diffusion (FD) node. The reset circuit is coupled to the ordinary FD node. The signal storage circuit is coupled to the ordinary FD node. The buffer circuit is coupled to the signal storage circuit. The signal storage circuit may store a PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation.
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公开(公告)号：US10566368B1
公开(公告)日：2020-02-18
申请号：US16101540
申请日：2018-08-13
发明人： Yang Wu , Fei-Xia Yu , Yu Hin Desmond Cheung
IPC分类号： H01L27/146
摘要： A pixel structure of an image sensor is provided and includes following units. A crystalline layer of a first doping type is formed on a substrate. A photodiode region is formed in the crystalline layer. A gate of a source follower transistor is formed on a top surface of the crystalline layer. A reset gate is formed on the top surface of the crystalline layer. A doped region of a second doping type is formed in the crystalline layer and formed between the reset gate and the gate of the source follower. The first doping type is different from the second doping type, and the photodiode region is connected to the doped region under the top surface of the crystalline layer as an anti-blooming path.
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公开(公告)号：US10152070B1
公开(公告)日：2018-12-11
申请号：US15665436
申请日：2017-08-01
发明人： Youngchul Sohn , Kwangoh Kim , Amit Mittra
摘要： An analog block implemented with a band-gap reference scheme for use in a device includes a mode control unit and a band-gap reference circuit. The mode control unit is configured to generate a mode selection signal associated with the operational mode of the device. The band-gap reference circuit includes a bias generator, an error amplifier, and a band-gap loop circuit. The bias generator is configured to provide a band-gap reference voltage in a first bias state when the device operates in a normal mode or in a second bias state when the device operates in a standby mode. The error amplifier is configured to generate an error voltage according to the bias voltage. The band-gap loop circuit is configured to provide a band-gap reference voltage according to the error voltage. First current flowing through the bias generator in the first bias state is larger than second current flowing through the bias generator in the second bias state.
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公开(公告)号：US10104321B1
公开(公告)日：2018-10-16
申请号：US15677598
申请日：2017-08-15
发明人： Youngchul Sohn , Kwangoh Kim , Hack soo Oh
IPC分类号： H04N5/361 , H04N5/369 , H04N5/376 , H04N5/3745 , H04N5/355
摘要： An image processing system for an image sensor includes an analog-to-digital conversion (ADC) unit that performs ADC on pixel signals, thereby generating digital pixel signals; a correlated double sampling (CDS) unit that performs CDS on the digital pixel signals; a black level estimation (BLE) unit that generates a negative offset voltage according to dark voltage obtained from CDS performed on estimating optical black pixels (OBPs) of a pixel array, the negative offset voltage being subtracted from the pixel signals before feeding the pixel signals to the ADC unit; and a black level compensation (BLC) unit that performs BLC on active pixels sensors (APSs) and the compensating OBPs of the pixel array.
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