公开(公告)号：US20050160234A1

公开(公告)日：2005-07-21

申请号：US10759922

申请日：2004-01-15

Applicant: Chris Newburn ,  Ram Huggahalli ,  Herbert Hum ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

Inventor： Chris Newburn ,  Ram Huggahalli ,  Herbert Hum ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0886 ,  G06F12/0802 ,  G06F12/0864 ,  G06F2212/401

Abstract: Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.

Abstract translation: 描述了能够处理压缩高速缓存行的信息量的多处理器计算系统的缓存一致性规则。 还描述了能够处理压缩高速缓存行的信息的多处理器计算系统。 多处理器计算系统包括用于与各种计算系统组件进行通信并用于压缩/解压缩高速缓存行的信息价值的多个集线器。 描述了能够根据高速缓存一致性规则来标记高速缓存线值的信息的处理器。 还描述了包括如上所述的集线器的处理器。

公开(公告)号：US20050144400A1

公开(公告)日：2005-06-30

申请号：US11069848

申请日：2005-02-28

Applicant: Herbert Hum ,  James Goodman

Inventor： Herbert Hum ,  James Goodman

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0813 ,  G06F12/0815 ,  G06F2212/2542

Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

Abstract translation: 本文描述的高速缓存一致性协议可用于维护系统的虚拟模型，其中虚拟模型不随系统配置改变而改变。 一般来说，虚拟模型是基于系统中的每个节点可以直接与系统中的其他节点通信的假设。 在一个实施例中，对于每个高速缓存行，高速缓存行的地址用于将节点指定为“家”节点，将所有其他节点指定为“对等”节点。 该协议指定一组消息，用于与线路的家庭节点通信，另一组消息用于与线路的对等节点进行通信。