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    Non-speculative distributed conflict resolution for a cache coherency protocol
    1.
    发明申请
    Non-speculative distributed conflict resolution for a cache coherency protocol 有权

    公开(公告)号：US20050237941A1

    公开(公告)日：2005-10-27

    申请号：US11165688

    申请日：2005-06-24

    Applicant: Robert Beers ,  Herbert Hum ,  James Goodman

    Inventor： Robert Beers ,  Herbert Hum ,  James Goodman

    IPC: G06F12/08 ,  H04L1/00

    CPC classification number: G06F12/0831 ,  G06F12/0813

    Abstract: A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

    Hierarchical directories for cache coherency in a multiprocessor system
    2.
    发明申请
    Hierarchical directories for cache coherency in a multiprocessor system 失效
    多处理器系统中高速缓存一致性的分层目录

    公开(公告)号：US20060253657A1

    公开(公告)日：2006-11-09

    申请号：US11482673

    申请日：2006-07-06

    Applicant: Herbert Hum ,  James Goodman

    Inventor： Herbert Hum ,  James Goodman

    IPC: G06F13/28 ,  G06F12/00

    CPC classification number: G06F12/0817 ,  G06F12/0813

    Abstract: Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory stores information related to data that has been exported through the agent. Because the import cache and the export directory only store data that has passed through the agent, not all data transferred within a system are tracked by a single import cache or export directory.

    Abstract translation: 使用导入缓存和/或导出目录与其中的代理来响应数据请求。 导入缓存存储通过代理程序导入的数据。 导出目录存储与通过代理导出的数据相关的信息。 因为导入缓存和导出目录只存储已经通过代理的数据，所以并不是系统中传输的所有数据都被单个导入缓存或导出目录跟踪。

    Hierarchical virtual model of a cache hierarchy in a multiprocessor system
    3.
    发明申请
    Hierarchical virtual model of a cache hierarchy in a multiprocessor system 有权

    公开(公告)号：US20060236038A1

    公开(公告)日：2006-10-19

    申请号：US11447384

    申请日：2006-06-05

    Applicant: Herbert Hum ,  James Goodman

    Inventor： Herbert Hum ,  James Goodman

    IPC: G06F12/00

    CPC classification number: G06F12/0813 ,  G06F12/0815 ,  G06F2212/2542

    Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

    Hierarchical virtual model of a cache hierarchy in a multiprocessor system
    4.
    发明申请
    Hierarchical virtual model of a cache hierarchy in a multiprocessor system 有权
    多处理器系统中缓存层次结构的分层虚拟模型

    公开(公告)号：US20050144400A1

    公开(公告)日：2005-06-30

    申请号：US11069848

    申请日：2005-02-28

    Applicant: Herbert Hum ,  James Goodman

    Inventor： Herbert Hum ,  James Goodman

    IPC: G06F12/08 ,  G06F12/00

    CPC classification number: G06F12/0813 ,  G06F12/0815 ,  G06F2212/2542

    Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

    Abstract translation: 本文描述的高速缓存一致性协议可用于维护系统的虚拟模型，其中虚拟模型不随系统配置改变而改变。 一般来说，虚拟模型是基于系统中的每个节点可以直接与系统中的其他节点通信的假设。 在一个实施例中，对于每个高速缓存行，高速缓存行的地址用于将节点指定为“家”节点，将所有其他节点指定为“对等”节点。 该协议指定一组消息，用于与线路的家庭节点通信，另一组消息用于与线路的对等节点进行通信。

    EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR
    5.
    发明申请
    EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR 有权
    加工商核心和加速器之间的有效数据传输

    公开(公告)号：US20150269074A1

    公开(公告)日：2015-09-24

    申请号：US14222792

    申请日：2014-03-24

    Applicant: Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

    Inventor： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

    IPC: G06F12/08 ,  G06F13/28 ,  G06F12/12

    CPC classification number: G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

    Abstract: A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

    Abstract translation: 处理器将输入数据写入共享高速缓存的高速缓存行，其中输入数据准备好由加速器操作。 然后通知加速器输入数据准备好进行处理。 处理器然后确定加速器的输出数据准备好被消耗，输出数据位于高速缓存行或共享高速缓存的附加高速缓存行，其中高速缓存线或附加高速缓存线包括设置的第一标志， 指示高速缓存行或附加高速缓存行被加速器修改，并且防止输出数据从高速缓存行或附加高速缓存行中移除，直到输出数据被处理器读取。 处理器从高速缓存行或附加高速缓存读取并处理输出数据。

    HYBRID INPUT/OUTPUT WRITE OPERATIONS
    6.
    发明申请
    HYBRID INPUT/OUTPUT WRITE OPERATIONS 审中-公开
    混合输入/输出写操作

    公开(公告)号：US20150113221A1

    公开(公告)日：2015-04-23

    申请号：US13997426

    申请日：2013-03-15

    Applicant: Herbert Hum ,  Chandra Joshi ,  Rahul Pal ,  Luke Chang

    Inventor： Herbert Hum ,  Chandra Joshi ,  Rahul Pal ,  Luke Chang

    IPC: G06F12/08

    CPC classification number: G06F12/0871 ,  G06F12/0875 ,  G06F2212/225 ,  G06F2212/452 ,  Y02D10/13

    Abstract: A first processor receives a write request from an input/output (I/O) device connected to the first processor. The first processor determines whether the write request satisfies an allocating write criterion. Responsive to determining that the write request satisfies the allocating write criterion, the first processor writes data associated with the write request to a cache of the first processor.

    Abstract translation: 第一处理器从连接到第一处理器的输入/输出（I / O）设备接收写请求。 第一处理器确定写入请求是否满足分配写入标准。 响应于确定写请求满足分配写标准，第一处理器将与写请求相关联的数据写入第一处理器的高速缓存。

    Software constructed strands for execution on a multi-core architecture
    7.
    发明授权
    Software constructed strands for execution on a multi-core architecture 有权
    用于在多核架构上执行的软件构造的线

    公开(公告)号：US08789031B2

    公开(公告)日：2014-07-22

    申请号：US11901644

    申请日：2007-09-18

    Applicant: Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

    Inventor： Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

    IPC: G06F9/45

    CPC classification number: G06F8/433

    Abstract: In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种形成指令串的软件控制方法。 软件可以包括用于获得包括多个基本块的超级块的代码的指令，为代码构建依赖性有向非循环图（DAG），将依赖性DAG的边缘耦合的分类节点排列成拓扑顺序，从节点形成线 基于硬件约束，规则约束和调度约束，并且生成链的可执行代码并将可执行代码存储在存储器中。 描述和要求保护其他实施例。

    SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX
    10.
    发明申请
    SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX 有权
    用于预留站负载依赖矩阵的系统和方法

    公开(公告)号：US20090328057A1

    公开(公告)日：2009-12-31

    申请号：US12164666

    申请日：2008-06-30

    Applicant: Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    Inventor： Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    IPC: G06F9/445

    CPC classification number: G06F9/3838 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3859

    Abstract: A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

    Abstract translation: 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。

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