公开(公告)号：US07512826B2

公开(公告)日：2009-03-31

申请号：US11110180

申请日：2005-04-20

申请人： William Joseph Armstrong ,  Michael J. Corrigan ,  Naresh Nayar ,  Scott Barnett Swaney

发明人： William Joseph Armstrong ,  Michael J. Corrigan ,  Naresh Nayar ,  Scott Barnett Swaney

IPC分类号： G06F1/12

CPC分类号： G06F1/14

摘要： A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.

摘要翻译： 在用于在逻辑分区的数据处理系统中提供虚拟时基的数据处理系统中公开了一种方法，装置和计算机程序产品。 为多个处理器核心中的每一个确定时基。 时基用于指示当前时间到其中确定时基的一个处理器内核。 对于处理器核心，时基同步在一起，使得每个处理器核心包括其自己的同步时基副本。 对于其中一个处理器核心，生成与同步时基不同的虚拟时基，但与同步时基的至少一部分保持同步。 处理器核心利用虚拟时基而不是同步的时基来指示处理器核心的当前时间。 同步的时基和虚拟时基的一部分保持同步在一起。

公开(公告)号：US20080256530A1

公开(公告)日：2008-10-16

申请号：US11735770

申请日：2007-04-16

申请人： William Joseph Armstrong ,  Robert J. Battista ,  David Anthony Larson ,  Naresh Nayar ,  Jonathan Ross Van Niewaal

发明人： William Joseph Armstrong ,  Robert J. Battista ,  David Anthony Larson ,  Naresh Nayar ,  Jonathan Ross Van Niewaal

IPC分类号： G06F9/445

CPC分类号： G06F9/45533 ,  G06F9/5077

摘要： An apparatus, program product and method for facilitating logical partition migrations between computers by determining if the firmware of the computers is compatible. A hypervisor of a source logical partition may transfer a token and compatibility table indicative of firmware running on the source computer. A hypervisor on the system of the target logical partition may compare the firmware indicated by the token with a token and/or compatibility table listing firmware versions compatible with the target computer. Conversely, a token of the target computer may be compared to a compatibility table associated with firmware that is compatible with the source computer. In either instance, a match may result in the migration of the logical partition. Alternatively, an absence of a match may result in the migration being prohibited.

摘要翻译： 一种用于通过确定计算机的固件是否兼容来促进计算机之间的逻辑分区迁移的装置，程序产品和方法。 源逻辑分区的管理程序可以传送指示在源计算机上运行的固件的令牌和兼容性表。 目标逻辑分区系统上的管理程序可以将令牌所指示的固件与列出与目标计算机兼容的固件版本的令牌和/或兼容性表进行比较。 相反，可以将目标计算机的令牌与与源计算机兼容的固件相关联的兼容性表进行比较。 在任一情况下，匹配可能导致逻辑分区的迁移。 或者，缺少匹配可能导致迁移被禁止。

公开(公告)号：US20080172554A1

公开(公告)日：2008-07-17

申请号：US11623219

申请日：2007-01-15

申请人： William J. Armstrong ,  Richard L. Arndt ,  David A. Larson ,  Naresh Nayar

发明人： William J. Armstrong ,  Richard L. Arndt ,  David A. Larson ,  Naresh Nayar

IPC分类号： G06F9/46 ,  G06F15/177

CPC分类号： G06F9/45541 ,  G06F9/45558 ,  G06F2009/4557

摘要： Methods, apparatus, and products are disclosed for controlling an operational mode for a logical partition on a computing system that include: receiving, in a hypervisor installed on the computing system, a processor compatibility mode for the logical partition and a firmware compatibility mode for the logical partition, the processor compatibility mode specifying a processor architecture version configured for the logical partition, and the firmware compatibility mode specifying a firmware architecture version configured for the logical partition; providing, by the hypervisor for the logical partition, a firmware interface in dependence upon the firmware compatibility mode; and providing, by the hypervisor for the logical partition, a processor interface in dependence upon the processor compatibility mode.

摘要翻译： 公开了用于控制计算系统上的逻辑分区的操作模式的方法，装置和产品，包括：在安装在计算系统上的管理程序中接收用于逻辑分区的处理器兼容性模式和用于 逻辑分区，指定为逻辑分区配置的处理器架构版本的处理器兼容性模式以及指定为逻辑分区配置的固件架构版本的固件兼容模式; 由逻辑分区的管理程序提供根据固件兼容性模式的固件接口; 以及由逻辑分区的管理程序提供依赖于处理器兼容性模式的处理器接口。

公开(公告)号：US20080168473A1

公开(公告)日：2008-07-10

申请号：US12050653

申请日：2008-03-18

申请人： William Joseph Armstrong ,  Naresh Nayar ,  Gregory Michael Nordstrom ,  Timothy Joseph Torzewski

发明人： William Joseph Armstrong ,  Naresh Nayar ,  Gregory Michael Nordstrom ,  Timothy Joseph Torzewski

IPC分类号： G06F13/00

CPC分类号： G06F9/5077 ,  G06F9/542 ,  G06F2209/543 ,  G06F2209/544

摘要： A logically-partitioned computer, program product and method utilize a flexible and adaptable communication interface between a partition and a partition manager, which permits optimal handling of partition management operations such as state change operations and the like over a wide variety of circumstances. In particular, a partition is permitted to indicate, in connection with a request to perform a partition management operation, whether an asynchronous notification should be generated or suppressed in association with the performance of the partition management operation by a partition manager. As a result, asynchronous notifications are selectively generated in association with the performance of partition management operations based upon indications in the requests made by partitions for such operations.

摘要翻译： 逻辑分区计算机，程序产品和方法利用分区和分区管理器之间的灵活且可适应的通信接口，其允许在各种情况下最佳地处理诸如状态改变操作等的分区管理操作。 特别地，允许分区结合执行分区管理操作的请求来指示是否应该由分区管理器执行分区管理操作来生成或抑制异步通知。 因此，基于由用于这种操作的分区所做的请求中的指示，与分区管理操作的执行相关联地选择性地生成异步通知。

公开(公告)号：US20080168254A1

公开(公告)日：2008-07-10

申请号：US12054538

申请日：2008-03-25

申请人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

发明人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

IPC分类号： G06F9/34

CPC分类号： G06F12/1036 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/683

摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

摘要翻译： 一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

公开(公告)号：US07275180B2

公开(公告)日：2007-09-25

申请号：US10418598

申请日：2003-04-17

申请人： William Joseph Armstrong ,  Naresh Nayar ,  Gary Ross Ricard

发明人： William Joseph Armstrong ,  Naresh Nayar ,  Gary Ross Ricard

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： G06F11/203 ,  G06F11/2028 ,  G06F11/2041 ,  G06F11/2046

摘要： Methods, systems, and articles of manufacture for replacement of a failing processor of a multi-processor system running at least one operating system are provided. In contrast to the prior art, the replacement may be performed by system firmware without intervention by the operating system (i.e., the replacement may be transparent to the operating system). For some embodiments, the multi-processor system may be logically partitioned and the methods may be utilized to replace one or more shared or dedicated processors assigned to a logical partition, transparent to an operating system running on the partition.

摘要翻译： 提供了用于替代运行至少一个操作系统的多处理器系统故障处理器的方法，系统和制品。 与现有技术相反，替换可以由系统固件执行，而不需要操作系统的干预（即，替换可能对操作系统是透明的）。 对于一些实施例，多处理器系统可以被逻辑地分区，并且该方法可以用于替换分配给逻辑分区的一个或多个共享或专用处理器，对于在分区上运行的操作系统是透明的。

公开(公告)号：US20070143565A1

公开(公告)日：2007-06-21

申请号：US11304136

申请日：2005-12-15

申请人： Michael Corrigan ,  Paul Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward Silha

发明人： Michael Corrigan ,  Paul Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward Silha

IPC分类号： G06F12/00

CPC分类号： G06F12/1036 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/683

摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

摘要翻译： 一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。

公开(公告)号：US20070079102A1

公开(公告)日：2007-04-05

申请号：US11241695

申请日：2005-09-30

申请人： William Armstrong ,  Naresh Nayar ,  Gary Ricard

发明人： William Armstrong ,  Naresh Nayar ,  Gary Ricard

IPC分类号： G06F12/00

CPC分类号： G06F11/1658 ,  G06F9/4856 ,  G06F9/5027 ,  G06F9/5077 ,  G06F11/2025 ,  G06F11/2028 ,  G06F11/2035 ,  G06F11/2043 ,  G06F2209/5011 ,  G06F2209/5021

摘要： Assigning a processor to a logical partition in a computer supporting multiple logical partitions that include assigning priorities to partitions, detecting a checkstop of a failing processor of a partition, retrieving the failing processor's state, replacing by a hypervisor the failing processor with a replacement processor from a partition having a priority lower than the priority of the partition of the failing processor, and assigning the retrieved state of the failing processor as the state of the replacement processor.

摘要翻译： 将处理器分配给支持多个逻辑分区的计算机中的逻辑分区，包括分配优先级到分区，检测分区的故障处理器的检查站，检索故障处理器的状态，由管理程序替换故障处理器与替换处理器 具有优先级低于故障处理器的分区的优先级的分区，以及将故障处理器的检索状态分配为替换处理器的状态。

公开(公告)号：US20070061612A1

公开(公告)日：2007-03-15

申请号：US11225653

申请日：2005-09-13

申请人： Daniel Henderson ,  Alongkorn Kitamorn ,  Wayne Lemmon ,  Naresh Nayar ,  Wade Ouren

发明人： Daniel Henderson ,  Alongkorn Kitamorn ,  Wayne Lemmon ,  Naresh Nayar ,  Wade Ouren

IPC分类号： G06F11/00

CPC分类号： G06F11/1008 ,  G11C29/76 ,  G11C29/88 ,  G11C2029/0411 ,  G11C2229/723

摘要： A method, apparatus, system, and signal-bearing medium that, in an embodiment, set uncorrectable error indicators in logical memory blocks in response to detecting an uncorrectable error in memory pages associated with the logical memory blocks. If the logical memory block is allocated to a hypervisor, the memory page may be deallocated in response to detection of the uncorrectable error. When an IPL of a partition is subsequently performed, a determination is made whether a logical memory block allocated to the partition previously encountered the uncorrectable error via the uncorrectable error indicator. If the logical memory block did previously encounter the uncorrectable error, the logical memory block is deallocated from the partition. In an embodiment, if spare memory exists, the logical memory block with the previously encountered uncorrectable error is replaced with the spare memory and the IPL of the partition is continued with the spare memory. If spare memory does not exist, the IPL of the partition is continued without the logical memory block that previously encountered the uncorrectable error. This allows a partition to IPL if it had not been able to because of a persistent uncorrectable error in its IPL path.

摘要翻译： 一种方法，装置，系统和信号承载介质，在一个实施例中，响应于检测到与逻辑存储器块相关联的存储器页面中的不可校正错误，在逻辑存储器块中设置不可校正的错误指示符。 如果逻辑存储器块被分配给管理程序，则可以响应于检测到不可校正的错误来释放存储器页面。 当随后执行分区的IPL时，确定分配给分区的逻辑存储器块先前是否经由不可校正的错误指示符遇到不可校正的错误。 如果逻辑内存块以前遇到不可纠正的错误，逻辑内存块将从分区中释放。 在一个实施例中，如果存在备用存储器，则具有先前遇到的不可校正错误的逻辑存储器块被备用存储器替换，并且分区的IPL与备用存储器一起继续。 如果备用内存不存在，则分区的IPL将继续，而没有先前遇到不可纠正错误的逻辑内存块。 如果由于IPL路径中持续存在不可纠正的错误，分区不能由IPL分区执行。

公开(公告)号：US07139855B2

公开(公告)日：2006-11-21

申请号：US10422426

申请日：2003-04-24

申请人： William Joseph Armstrong ,  Naresh Nayar

发明人： William Joseph Armstrong ,  Naresh Nayar

IPC分类号： G06F12/00

CPC分类号： G06F9/526

摘要： A method, apparatus, system, and signal-bearing medium that in an embodiment set a resource indicator to indicate that a processor is using a resource in a logically-partitioned electronic device, determine whether a current partition in the logically-partitioned electronic device owns the resource, and clear the resource indicator after the processor is done using the resource. When a partition gives up ownership of a resource, a resource ownership state is changed to indicate that the partition does not own a resource, and the partition waits to continue executing until other processors have cleared their respective resource indicators. In an embodiment, the resource indicator is in a cache line that is local to the processor, which allows resources to be dynamically allocated with improved performance.

摘要翻译： 一种方法，装置，系统和信号承载介质，其在一个实施例中设置资源指示符以指示处理器正在逻辑分区的电子设备中使用资源，确定逻辑分区的电子设备中的当前分区是否拥有 资源，并在处理器完成资源后清除资源指示符。 当分区放弃资源的所有权时，将更改资源所有权状态以指示分区不拥有资源，并且分区等待继续执行，直到其他处理器清除其各自的资源指示符。 在一个实施例中，资源指示符位于处理器本地的高速缓存行中，这允许以改进的性能动态分配资源。