Integrated filler capacitor cell device and corresponding manufacturing method

    公开(公告)号:US11621222B2

    公开(公告)日:2023-04-04

    申请号:US17173275

    申请日:2021-02-11

    Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

    Device and method for allocating intermediate data from an artificial neural network

    公开(公告)号:US11609851B2

    公开(公告)日:2023-03-21

    申请号:US17229161

    申请日:2021-04-13

    Abstract: According to one aspect, a method for determining, for a memory allocation, placements in a memory area of data blocks generated by a neural network, comprises a development of an initial sequence of placements of blocks, each placement being selected from several possible placements, the initial sequence being defined as a candidate sequence, a development of at least one modified sequence of placements from a replacement of a given placement of the initial sequence by a memorized unselected placement, and, if the planned size of the memory area obtained by this modified sequence is less than that of the memory area of the candidate sequence, then this modified sequence becomes the candidate sequence, the placements of the blocks for the allocation being those of the placement sequence defined as a candidate sequence once each modified sequence has been developed.

    Direct memory access
    57.
    发明授权

    公开(公告)号:US11593289B2

    公开(公告)日:2023-02-28

    申请号:US16516988

    申请日:2019-07-19

    Abstract: A memory contains a linked list of records representative of a plurality of data transfers via a direct memory access control circuit. Each record is representative of parameters of an associated data transfer of the plurality of data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.

    Method and apparatus for converting a digital image

    公开(公告)号:US11568515B2

    公开(公告)日:2023-01-31

    申请号:US17361783

    申请日:2021-06-29

    Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.

    Time domains synchronization in a system on chip

    公开(公告)号:US11552777B2

    公开(公告)日:2023-01-10

    申请号:US17457354

    申请日:2021-12-02

    Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

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