公开(公告)号：US09928069B2

公开(公告)日：2018-03-27

申请号：US14137232

申请日：2013-12-20

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30076

Abstract: A hazard check instruction has operands that specify addresses of vector elements to be read by first and second vector memory operations. The hazard check instruction outputs a dependency vector identifying, for each element position of the first vector corresponding to the first vector memory operation, which element position of the second vector that the element of the first vector depends on (if any). In an embodiment, the addresses of the vector memory operations are specified using a base address for each vector memory operation and a vector that is shared by both vector memory operations. In an embodiment, the operands may include predicates for one or both of the vector memory operations, indicating which vector elements are active. The dependency vector may be qualified by the predicates, indicating dependencies only for active elements.

公开(公告)号：US09442734B2

公开(公告)日：2016-09-13

申请号：US14177378

申请日：2014-02-11

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/34 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC classification number: G06F9/345 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3836

Abstract: In an embodiment, a processor may include a completion time determination circuit. The completion time determination circuit may be configured to receive one or more source operands of a vector memory operation used to produce the addresses of the vector elements accessed by the vector memory operation. The completion time determination circuit may be configured to determine a completion time for the vector memory operation (e.g. based on a number of TLB accesses, a number of cache accesses, and/or other aspects of the vector memory operation). The completion time determination circuit may provide the completion time to an issue circuit, which may use the completion time to schedule operations dependent on the vector memory operation, if any.

Abstract translation: 在一个实施例中，处理器可以包括完成时间确定电路。 完成时间确定电路可以被配置为接收用于产生由向量存储器操作访问的向量元素的地址的向量存储器操作的一个或多个源操作数。 完成时间确定电路可以被配置为确定向量存储器操作的完成时间（例如，基于多个TLB访问，多个高速缓存访​​问和/或向量存储器操作的其他方面）。 完成时间确定电路可以向发布电路提供完成时间，其可以使用完成时间来调度取决于向量存储器操作的操作（如果有的话）。

公开(公告)号：US20150227368A1

公开(公告)日：2015-08-13

申请号：US14177378

申请日：2014-02-11

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/345 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3836

Abstract: In an embodiment, a processor may include a completion time determination circuit. The completion time determination circuit may be configured to receive one or more source operands of a vector memory operation used to produce the addresses of the vector elements accessed by the vector memory operation. The completion time determination circuit may be configured to determine a completion time for the vector memory operation (e.g. based on a number of TLB accesses, a number of cache accesses, and/or other aspects of the vector memory operation). The completion time determination circuit may provide the completion time to an issue circuit, which may use the completion time to schedule operations dependent on the vector memory operation, if any.

Abstract translation: 在一个实施例中，处理器可以包括完成时间确定电路。 完成时间确定电路可以被配置为接收用于产生由向量存储器操作访问的向量元素的地址的向量存储器操作的一个或多个源操作数。 完成时间确定电路可以被配置为确定向量存储器操作的完成时间（例如，基于多个TLB访问，多个高速缓存访​​问和/或向量存储器操作的其他方面）。 完成时间确定电路可以向发布电路提供完成时间，其可以使用完成时间来调度取决于向量存储器操作的操作（如果有的话）。

公开(公告)号：US20150089192A1

公开(公告)日：2015-03-26

申请号：US14034680

申请日：2013-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30 ,  G06F15/78

CPC classification number: G06F15/78 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/3013

Abstract: In an embodiment, a processor may be configured to dynamically infer one or more attributes of input and/or output registers of an instruction, given the attributes corresponding to at least one input registers. The inference may be made at the issue circuit/stage of the processor, for those registers that do not have attribute information at the issue circuit/stage. In an embodiment, the processor may also include a register attribute tracker configured to track attributes of registers prior to the issue stage of the processor pipeline. The processor may feed back, to the register attribute tracker, inferred attributes and the register addresses of the registers to which the inferred attributes apply. The register attribute tracker may be configured to may associate the inferred attribute with the identified register attribute tracker may also be configured to infer input register attributes from other input register attributes.

Abstract translation: 在一个实施例中，给定与至少一个输入寄存器对应的属性，处理器可以被配置为动态地推断指令的输入和/或输出寄存器的一个或多个属性。 推理可以在处理器的发布电路/阶段进行，对于那些在发布电路/阶段没有属性信息的寄存器。 在一个实施例中，处理器还可以包括配置为在处理器流水线的发布阶段之前跟踪寄存器的属性的寄存器属性跟踪器。 处理器可以向注册属性跟踪器反馈推断的属性和推断的属性适用的寄存器的寄存器地址。 寄存器属性跟踪器可以被配置为可以将推断的属性与所识别的寄存器属性跟踪器相关联，还可以被配置为从其他输入寄存器属性推断输入寄存器属性。

公开(公告)号：US20150089190A1

公开(公告)日：2015-03-26

申请号：US14034640

申请日：2013-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30105 ,  G06F9/3013

Abstract: In an embodiment, a processor includes a register attribute tracker configured to track one or more attributes corresponding to registers. The register attribute tracker may track the attributes associated with the registers when those registers are used as output registers of instructions that explicitly define the attributes and, if the register attribute tracker has a tracked attribute associated with an input register of an instruction that does not explicitly define the attribute, the register attribute tracker may annotate the instruction with an attribute and/or associate an attribute with the output register of the instruction in the register attribute tracker.

Abstract translation: 在一个实施例中，处理器包括配置为跟踪与寄存器对应的一个或多个属性的寄存器属性跟踪器。 当这些寄存器用作明确定义属性的指令的输出寄存器时，寄存器属性跟踪器可以跟踪与寄存器相关联的属性，并且如果寄存器属性跟踪器具有与未明确指定的指令的输入寄存器相关联的跟踪属性 定义属性，寄存器属性跟踪器可以使用属性注释指令和/或将属性与注册属性跟踪器中的指令的输出寄存器相关联。

公开(公告)号：US20150058832A1

公开(公告)日：2015-02-26

申请号：US14532846

申请日：2014-11-04

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/45

CPC classification number: G06F8/433 ,  G06F8/445 ,  G06F8/447

Abstract: System and methods for the parallelization of software applications are described. In some embodiments, a compiler may automatically identify within source code dependencies of a function called by another function. A persistent database may be generated to store identified dependencies. When calls the function are encountered within the source code, the persistent database may be checked, and a parallelized implementation of the function may be employed dependent upon the dependency indicated in the persistent database.

Abstract translation: 描述了软件应用并行化的系统和方法。 在一些实施例中，编译器可以自动识别由另一功能调用的函数的源代码依赖性。 可以生成持久性数据库以存储所识别的依赖性。 当在源代码中遇到调用函数时，可以检查持久性数据库，并且可以依赖于持久性数据库中指示的依赖性来采用该函数的并行实现。

公开(公告)号：US20140289502A1

公开(公告)日：2014-09-25

申请号：US14218475

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/3838

Abstract: Systems, apparatuses and methods for utilizing enhanced vector true/false instructions. The enhanced vector true/false instructions generate enhanced predicates to correspond to the request element width and/or vector size. A vector true instruction generates an enhanced predicate where all elements supported by the processing unit are active. A vector false instruction generates an enhanced predicate where all elements supported by the processing unit are inactive. The enhanced predicate specifies the requested element width in addition to designating the element selectors.

Abstract translation: 用于利用增强的向量真/假指令的系统，装置和方法。 增强的向量真/假指令生成增强的谓词以对应于请求元素宽度和/或向量大小。 向量真指令生成增强谓词，其中处理单元支持的所有元素都处于活动状态。 向量假指令生成增强谓词，其中处理单元支持的所有元素都处于非活动状态。 增强谓词除了指定元素选择器之外还指定了所请求的元素宽度。

公开(公告)号：US20140289497A1

公开(公告)日：2014-09-25

申请号：US14218464

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3838

Abstract: Systems, apparatuses and methods for utilizing enhanced Macroscalar comparison operations which take an enhanced predicate operand that designates the element width and which elements are to be processed. The element width and the number of elements per vector are determined at run-time rather than being defined in the architectural definition of the instruction. This enables additional parallelism when processing smaller-sized data. The instruction performs the requested operation on the elements specified by the enhanced predicate, assuming an element-width also specified by the enhanced predicate, and returns the result as an enhanced predicate corresponding to the result of the comparison.

Abstract translation: 用于利用增强的宏观比较操作的系统，装置和方法，其采用指定元素宽度和要处理哪些元素的增强谓词操作数。 元素宽度和每个向量的元素数量在运行时确定，而不是在指令的体系结构定义中定义。 这可以在处理较小尺寸的数据时实现额外的并行性。 指令对增强谓词指定的元素执行所请求的操作，假设由增强谓词指定的元素宽度，并将结果作为与比较结果相对应的增强谓词返回。

公开(公告)号：US08560815B2

公开(公告)日：2013-10-15

申请号：US13628857

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/305

CPC classification number: G06F8/4441 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a Boolean operation on another input vector dependent upon the input vector and the control vector.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使得处理器根据输入向量和控制向量对另一输入向量执行布尔运算。

公开(公告)号：US20130024672A1

公开(公告)日：2013-01-24

申请号：US13630328

申请日：2012-09-28

Applicant: APPLE INC.

Inventor： Jeffry E. Gonion

IPC: G06F9/302

CPC classification number: G06F8/4441 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive a basis vector, an operand vector, a selection vector, and a control vector are disclosed. The executed instructions may also cause the processor to perform a wrapping propagate operation dependent upon the input vectors.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收基本向量，操作数向量，选择向量和控制向量的指令。 执行的指令还可以使得处理器根据输入向量来执行环绕传播操作。