公开(公告)号：US10169573B2

公开(公告)日：2019-01-01

申请号：US15284830

申请日：2016-10-04

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

IPC: G06F21/62 ,  G06F21/52 ,  G06F9/30 ,  G06F9/46

Abstract: A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level.

公开(公告)号：US10025923B2

公开(公告)日：2018-07-17

申请号：US14935504

申请日：2015-11-09

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite ,  Simon John Craske

IPC: G06F21/52 ,  G06F9/30 ,  G06F9/46

Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.

公开(公告)号：US09292036B2

公开(公告)日：2016-03-22

申请号：US13901771

申请日：2013-05-24

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  Thomas Sean Houlihane

IPC: G06F15/16 ,  G06F1/12 ,  H04L12/40 ,  G06F13/42

CPC classification number: G06F1/12 ,  G06F13/4282 ,  H04L12/40019

Abstract: A data processing apparatus and method provide communication between a master device operating from a master clock signal and a slave device operating from a slave clock signal asynchronous to the master clock signal. An interface transfers packets between the master device and the slave device. A slave clock replica generator associated with the master device generates a slave clock replica that controls timing of transmission of packets by the master device over the interface. A sync request transfer is issued over the interface and has a property identifiable by the slave device irrespective of whether the sync request transfer is synchronized with the slave clock signal. In response, the slave device issues a sync response transfer indicative of at least a frequency of the slave clock signal, and the slave clock replica generator determines at least the frequency of the slave clock replica from that sync transfer.

Abstract translation: 数据处理装置和方法提供从主时钟信号操作的主设备与从主时钟信号异步的从时钟信号操作的从设备之间的通信。 接口在主设备和从设备之间传送报文。 与主设备相关联的从时钟副本生成器产生从时钟副本，其控制由主设备通过接口传送分组的定时。 通过接口发出同步请求传送，并具有由从设备可识别的属性，而不管同步请求传输是否与从时钟信号同步。 作为响应，从设备发出指示从时钟信号的至少频率的同步响应传输，并且从时钟副本生成器至少从该同步传送确定从时钟副本的频率。