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    Multiple voltage mode pre-charging and selective level shifting
    51.
    发明授权
    Multiple voltage mode pre-charging and selective level shifting 有权
    多电压模式预充电和选择电平转换

    公开(公告)号：US07800407B1

    公开(公告)日：2010-09-21

    申请号：US12492938

    申请日：2009-06-26

    申请人： Amit Agarwal ,  Steven K. Hsu ,  Ram K. Krishnamurthy

    发明人： Amit Agarwal ,  Steven K. Hsu ,  Ram K. Krishnamurthy

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018521

    摘要： To pre-charge a node to one of first and second voltage levels in response to inputs received at the corresponding voltage level, to selectively level shift the node from the first voltage level to the second voltage level when in a first voltage mode, and to maintain the node at the second voltage level when in a second voltage mode. Level shifting from first voltage level may be performed within one gate stage that may be bypassed when in the second voltage mode. The node may be discharged with no delay difference between the first and second voltage modes. Inputs may include a clock signal, which may be received at either of the first and second voltage levels without level shifting the clock signal. A circuit may be implemented with a multi-core processor system to permit selective voltage mode operation of the cores.

    摘要翻译： 为了响应于在相应电压电平处接收到的输入，将节点预充电到第一和第二电压电平之一，以便当在第一电压模式下选择性地将节点从第一电压电平移位到第二电压电平，并且 当处于第二电压模式时，将节点保持在第二电压电平。 可以在一个门级内执行从第一电压电平的电平转换，当处于第二电压模式时，可能被旁路。 可以在第一和第二电压模式之间没有延迟差放电节点。 输入可以包括时钟信号，其可以在第一和第二电压电平中的任何一个处接收，而不会对时钟信号进行电平移位。 电路可以用多核处理器系统来实现，以允许芯的选择性电压模式操作。

    Full-rail, dual-supply global bitline accelerator CAM circuit
    53.
    发明授权
    Full-rail, dual-supply global bitline accelerator CAM circuit 有权
    全轨，双电源全局位线加速器CAM电路

    公开(公告)号：US07426127B2

    公开(公告)日：2008-09-16

    申请号：US11642838

    申请日：2006-12-21

    申请人： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

    发明人： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04

    摘要： A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first and second local bit lines and the global bit line. The global bit line accelerator sets the second local bit line to a first logical value depending on a signal from the first local bit line. In this way, the global bit line accelerator accelerates the evaluation phase of operation of the second local bit line.

    摘要翻译： 内容寻址存储器电路包括耦合到第一存储器位置的第一本地位线，耦合到第二存储器位置的第二本地位线，耦合到第一和第二局部位线的全局位线和全局位线加速器 耦合到第一和第二局部位线和全局位线。 全局位线加速器根据来自第一局部位线的信号将第二本地位线设置为第一逻辑值。 以这种方式，全局位线加速器加速第二局部位线的运算的评估阶段。

    Image manipulation for videos and still images
    54.
    发明申请
    Image manipulation for videos and still images 审中-公开
    视频和静止图像的图像处理

    公开(公告)号：US20080181507A1

    公开(公告)日：2008-07-31

    申请号：US12011705

    申请日：2008-01-28

    申请人： Chandan Gope ,  Amit Agarwal ,  Vaidhi Nathan ,  Alexander Bovyrin ,  Ilya Popov ,  Lev Afraimovich

    发明人： Chandan Gope ,  Amit Agarwal ,  Vaidhi Nathan ,  Alexander Bovyrin ,  Ilya Popov ,  Lev Afraimovich

    IPC分类号： G06K9/46 ,  G06K9/03 ,  G06K9/40 ,  G06K9/36

    CPC分类号： H04N5/272 ,  G06T5/002 ,  G06T7/11 ,  G06T7/194 ,  G06T11/60 ,  G06T2207/20012 ,  H04N5/144

    摘要： In an embodiment, an image is received having a first portion and one or more other portions. The one or more other portions are replaced with one or more other images. The replacing of the one or more portions results in an image including the first portion and the one or more other images. In an embodiment, the background of an image is replaced with another background. In an embodiment, the foreground is extracted by identifying the background based on an image of the background without any foreground. In an embodiment, the foreground is extracted by identifying portions of the image that have characteristics that are expected to be associated with the background and characteristics that are expected to be associated with foreground. In an embodiment any of the images can be still images. In an embodiment, any of the images are video images.

    摘要翻译： 在一个实施例中，接收具有第一部分和一个或多个其它部分的图像。 一个或多个其它部分被一个或多个其他图像替换。 更换一个或多个部分导致包括第一部分和一个或多个其他图像的图像。 在一个实施例中，图像的背景被替换为另一背景。 在一个实施例中，通过基于背景的图像识别背景来提取前景，而没有任何前景。 在一个实施例中，通过识别具有预期与预期与前景相关联的背景和特征的特征的图像的部分来提取前景。 在一个实施例中，任何图像可以是静止图像。 在一个实施例中，任何图像是视频图像。

    Full-rail, dual-supply global bitline accelerator CAM circuit
    55.
    发明申请
    Full-rail, dual-supply global bitline accelerator CAM circuit 有权

    公开(公告)号：US20080151588A1

    公开(公告)日：2008-06-26

    申请号：US11642838

    申请日：2006-12-21

    申请人： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

    发明人： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04

    摘要： A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first and second local bit lines and the global bit line. The global bit line accelerator sets the second local bit line to a first logical value depending on a signal from the first local bit line. In this way, the global bit line accelerator accelerates the evaluation phase of operation of the second local bit line.

    Reducing the number of block masks required for programming multiple access control list in an associative memory
    56.
    发明授权
    Reducing the number of block masks required for programming multiple access control list in an associative memory 有权
    减少关联存储器中编程多个访问控制列表所需的块掩码数

    公开(公告)号：US07249228B1

    公开(公告)日：2007-07-24

    申请号：US10791632

    申请日：2004-03-01

    申请人： Amit Agarwal ,  Venkateshwar Rao Pullela ,  Qizhong Chen

    发明人： Amit Agarwal ,  Venkateshwar Rao Pullela ,  Qizhong Chen

    IPC分类号： G06F12/00

    CPC分类号： G06F21/6218 ,  G06F2221/2141 ,  H04L45/7453 ,  H04L63/0263

    摘要： Mechanisms for reducing the number of block masks required for programming multiple access control lists in an associative memory are disclosed. A combined ordering of masks corresponding to multiple access control lists (ACLs) is typically identified, with the multiple ACLs including n ACLs. An n-dimensional array is generated, wherein each axis of the n-dimensional array corresponds to masks in their requisite order of a different one of the multiple ACLs. The n-dimensional array progressively identifies numbers of different masks required for subset orderings of masks required for subsets of the multiple ACLs. The n-dimensional array is traversed to identify a sequence of masks corresponding to a single ordering of masks including masks required for each of the multiple ACLs.

    摘要翻译： 公开了减少在关联存储器中编程多个访问控制列表所需的块掩码的数量的机制。 通常标识与多个访问控制列表（ACL）对应的掩码的组合排序，其中多个ACL包括n个ACL。 生成n维阵列，其中n维阵列的每个轴以其多个ACL中不同一个的必要顺序对应于掩码。 n维阵列渐进地标识多个ACL的子集所需的掩码的子集排序所需的不同掩码的数量。 遍历n维阵列以识别对应于包括多个ACL中的每一个所需的掩码的掩码的单个排序的掩码序列。

    Low leakage and leakage tolerant stack free multi-ported register file
    58.
    发明申请
    Low leakage and leakage tolerant stack free multi-ported register file 有权
    低泄漏和容错堆栈自由多端口寄存器文件

    公开(公告)号：US20060067136A1

    公开(公告)日：2006-03-30

    申请号：US10953202

    申请日：2004-09-28

    申请人： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

    发明人： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

    IPC分类号： G11C7/10

    CPC分类号： G11C11/413 ,  G11C2207/007

    摘要： A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.

    摘要翻译： 一种设备包括多个存储单元。 每个存储单元包括耦合到位线的晶体管堆叠。 访问模式期间位线上的电荷值表示存储在访问存储单元中的数据的值。 在非访问模式期间，晶体管堆叠的所有晶体管都被关闭以节省功率。 无论存储在存储器单元中的数据的值如何，晶体管都截止。