公开(公告)号：US07626462B1

公开(公告)日：2009-12-01

申请号：US11415578

申请日：2006-05-02

申请人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr. ,  Stephen T. Janesch

发明人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr. ,  Stephen T. Janesch

IPC分类号： H03L7/00

CPC分类号： H03L7/23 ,  H03J1/005 ,  H03J7/065 ,  H03L7/1974

摘要： A fractional-N based Automatic Frequency Control (AFC) system for a mobile terminal is provided. In general, automatic frequency control is implemented in a frequency synthesizer to correct or compensate for a frequency error of an associated reference oscillator. The frequency synthesizer includes a first fractional-N phase-locked loop (FN-PLL) generating a baseband clock signal used by a baseband processor of the mobile terminal, a second FN-PLL generating a receiver local oscillator signal used by a receiver of the mobile terminal to downconvert a received radio frequency signal to a desired frequency, and a translational PLL generating a transmitter local oscillator signal used by a transmitter of the mobile terminal to provide a radio frequency transmit signal. The automatic frequency control is performed by applying a digital correction value, which is preferably multiplicative, to fractional-N dividers of the first and second FN-PLLs.

摘要翻译： 提供了一种用于移动终端的基于分数N的自动频率控制（AFC）系统。 通常，在频率合成器中实现自动频率控制以校正或补偿相关参考振荡器的频率误差。 频率合成器包括产生由移动终端的基带处理器使用的基带时钟信号的第一小数N锁相环（FN-PLL），第二FN-PLL产生由接收机使用的接收机本地振荡器信号 移动终端将所接收的射频信号下变频到期望的频率，以及平移PLL，其生成由移动终端的发射机使用以提供射频发射信号的发射机本地振荡器信号。 通过将优选乘法的数字校正值应用于第一和第二FN-PLL的分数N分频器来执行自动频率控制。

公开(公告)号：US07098754B2

公开(公告)日：2006-08-29

申请号：US11047258

申请日：2005-01-31

申请人： Scott Robert Humphreys ,  Ryan Lee Bunch ,  Barry Travis Hunt, Jr. ,  Alexander Wayne Hietala

发明人： Scott Robert Humphreys ,  Ryan Lee Bunch ,  Barry Travis Hunt, Jr. ,  Alexander Wayne Hietala

IPC分类号： H03C3/00 ,  H04L27/20

CPC分类号： H03L7/1976 ,  H03C3/0966 ,  H03L7/23 ,  H03L2207/12

摘要： A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

摘要翻译： 提供了一个分数N偏移锁相环（FN-OPLL）。 FN-OPLL包括分数分频器，相位检测器，环路滤波器，压控振荡器（VCO）和反馈电路。 组合器电路组合初始分数除法值和调制信号以提供组合分数除数值。 基于组合分数除法，分数N分频器划分参考频率，并向相位检测器提供分频参考频率。 相位检测器将分频参考频率的相位与反馈信号的相位进行比较，以提供比较信号。 比较信号由环路滤波器滤波，以向VCO提供控制信号，其中控制信号控制VCO的输出信号的频率。 输出信号由反馈电路处理，以将反馈信号提供给相位检测器。