公开(公告)号：US20180191360A1

公开(公告)日：2018-07-05

申请号：US15739690

申请日：2015-06-26

申请人： Olympus Corporation

发明人： John B. Groe ,  Kishore RAMA RAO

IPC分类号： H03L7/099 ,  H03B5/12 ,  H03C3/09

CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03C3/0966 ,  H03C3/0983 ,  H03L2207/10 ,  H03L2207/12

摘要： Systems and methods are provided in which an offset phase-locked loop (PLL) system can be configured as part of a radio frequency transmitter. The PLL can include a phase detection circuit including a first input configured to receive an information signal and a second input configured to receive a feedback signal; a charge pump including an input coupled to the phase detection circuit and an output; a filter including an input coupled to the output of the charge pump; a voltage-controlled oscillator coupled to the charge pump and including an LC tank circuit comprising an inductive element and a capacitive element, wherein the inductive element of the LC tank circuit comprises the antenna; and a feedback path.

公开(公告)号：US09306497B2

公开(公告)日：2016-04-05

申请号：US14323278

申请日：2014-07-03

申请人： Associated Universities, Inc.

发明人： Richard D. Scott ,  Walter F. Brisken ,  Robert E. Long

IPC分类号： H03L7/06 ,  H03B21/02 ,  H03L7/16

CPC分类号： H03B21/025 ,  H03B2200/0054 ,  H03L7/16 ,  H03L2207/12

摘要： A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency.

摘要翻译： 公开了一种可变频率合成器和输出可变频率的方法。 合成器包括第一参考频率，接收第一参考频率并输出调谐频率的直接数字合成器（DDS），接收调谐频率的可变频率梳发生器，并输出由多个梳状线组成的可变频率梳， 接收可变频梳和来自振荡器并输出中频的信号的混频器，接收第二参考频率和中频的锁相环（PLL）和输出锁相信号，并且振荡器接收锁相信号和 输出可变合成频率。

公开(公告)号：US09231600B1

公开(公告)日：2016-01-05

申请号：US14791321

申请日：2015-07-03

申请人： PMC-SIERRA US, INC.

发明人： Hormoz Djahanshahi ,  William Michael Lye

IPC分类号： H03L7/18 ,  H03L7/093 ,  H03L7/07 ,  H03L7/087 ,  H03L7/099 ,  H03L7/197

CPC分类号： H03L7/07 ,  H03L7/087 ,  H03L7/099 ,  H03L7/185 ,  H03L7/1974 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/12 ,  H04L7/0025 ,  H04L7/0331 ,  H04L7/0332

摘要： A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

公开(公告)号：US08995506B2

公开(公告)日：2015-03-31

申请号：US13977299

申请日：2010-12-31

申请人： Anton Willem Roodnat ,  Hans Van Driest ,  Jan Hendrik Haanstra

发明人： Anton Willem Roodnat ,  Hans Van Driest ,  Jan Hendrik Haanstra

IPC分类号： H03B21/00 ,  H03L7/16

CPC分类号： H03B21/00 ,  H03L7/16 ,  H03L2207/12 ,  H04B1/40 ,  H04B1/408

摘要： Disclosed is a transceiver including a sub-sampling based frequency synthesizer with a sampling frequency fsmp, configured to generate M different output signals 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception. M is an integer greater than 4, each output signal has a corresponding predefined frequency. The predefined frequencies are within a frequency band with a predefined bandwidth CFR. CFR is greater than fsmp. The frequency synthesizer includes a frequency shift unit configured for shifting a version of the output signal over a predefined frequency shift fshift to obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer, wherein −fsmp/2≦fshift≦+fsmp/2. The frequency shift unit is configured to use for the generation of each of the N different output signals a corresponding predefined frequency shift fshift.

摘要翻译： 公开了一种收发器，其包括具有采样频率fsmp的基于子采样的频率合成器，被配置为产生用于传输的载波信号的M个不同的输出信号和/或具有用于接收的信道频率的信号。 M是大于4的整数，每个输出信号具有相应的预定频率。 预定义的频率在具有预定带宽CFR的频带内。 CFR大于fsmp。 所述频率合成器包括：频移单元，被配置为在预定义的频移频率上移位输出信号的版本，以获得提供给基于子采样的频率合成器的采样单元的频移信号，其中-fsmp / 2＆nlE ; fshift＆nlE; + fsmp / 2。 频移单元被配置为用于产生相应的预定频移位移的N个不同输出信号中的每一个。

公开(公告)号：US20150028926A1

公开(公告)日：2015-01-29

申请号：US14513644

申请日：2014-10-14

申请人： Renesas Mobile Corporation

发明人： Takahiro NAKAMURA

IPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/099 ,  H03L7/185

CPC分类号： H03B5/1265 ,  H03B5/1212 ,  H03B5/1228 ,  H03L7/02 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0991 ,  H03L7/1075 ,  H03L7/185 ,  H03L2207/05 ,  H03L2207/12 ,  H03L2207/50 ,  H04B1/16

摘要： The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

摘要翻译： 本发明提供能够实现DNL降低的数字控制振荡器装置。 数字控制振荡器装置包括例如在振荡输出节点之间并联耦合的放大器电路块，线圈元件和多个整体电容器单元。 每个单体电容器单元设置有电容元件，以及开关，其选择是否应允许电容元件作为振荡频率的设定参数贡献。 开关由从解码器电路延伸的开/关控制线驱动。 开关控制线被屏蔽部分屏蔽在振荡输出节点之间。

公开(公告)号：US08816777B2

公开(公告)日：2014-08-26

申请号：US13236841

申请日：2011-09-20

申请人： Tomany Szilagyi

发明人： Tomany Szilagyi

IPC分类号： H03L7/087 ,  H03L7/22 ,  H03B21/00 ,  H03L7/08

CPC分类号： H03L7/08 ,  H03L7/0805 ,  H03L7/104 ,  H03L7/23 ,  H03L2207/12

摘要： A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer.

摘要翻译： 公开了一种微波合成器，其可以产生低相位噪声和高频分辨率微波信号。微波合成器可以包括粗调谐环路，可以采用粗调回路来产生具有粗调频率的第一信号。 粗调谐环路可以具有第一压控振荡器（VCO）。 可以采用输出回路来产生具有微调频率的第二信号。 输出环路可以具有第二VCO。 混频器可以被配置为耦合粗调回路和输出回路。 可以采用混频器来减去第一和第二信号。 参考频率源可以耦合到粗调回路和输出回路以提供用于微波合成器的参考信号。

公开(公告)号：US08779814B2

公开(公告)日：2014-07-15

申请号：US13947515

申请日：2013-07-22

申请人： Associated Universities, Inc.

发明人： Richard D. Scott ,  Walter F. Brisken ,  Robert E. Long

IPC分类号： H03L7/06 ,  H03L7/16

CPC分类号： H03B21/025 ,  H03B2200/0054 ,  H03L7/16 ,  H03L2207/12

摘要： A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency.

摘要翻译： 公开了一种可变频率合成器和输出可变频率的方法。 合成器包括第一参考频率，接收第一参考频率并输出调谐频率的直接数字合成器（DDS），接收调谐频率的可变频率梳发生器，并输出由多个梳状线组成的可变频率梳， 接收可变频梳和来自振荡器并输出中频的信号的混频器，接收第二参考频率和中频的锁相环（PLL）和输出锁相信号，并且振荡器接收锁相信号和 输出可变合成频率。

公开(公告)号：US08595538B2

公开(公告)日：2013-11-26

申请号：US12041543

申请日：2008-03-03

申请人： Yifeng Zhang ,  Peiqi Xuan ,  Kanyu Cao ,  Xiaodong Jin

发明人： Yifeng Zhang ,  Peiqi Xuan ,  Kanyu Cao ,  Xiaodong Jin

IPC分类号： G06F1/00 ,  G06F1/04 ,  H03L7/06

CPC分类号： H03L7/099 ,  H03L2207/12

摘要： In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.

摘要翻译： 在本发明的实施例中，公开了一种时钟发生器电路，其包括响应于参考频率并且可操作以产生单个时钟频率和时钟信号正交输出频率的锁相环（PLL）和时钟信号 相位输出与时钟信号的频率正交输出频率和时钟信号同相输出频率是单个时钟频率频率的一部分。 PLL包括产生单个时钟频率的单个压控振荡器（VCO）。 多个分频器被包括在时钟发生器电路中，并且响应于时钟信号正交输出频率和时钟信号同相输出频率，并且产生多个时钟频率，每个时钟频率是唯一的频率，每个分频器 产生输出，多个分频器的最终输出与参考频率同步。

公开(公告)号：US20130207700A1

公开(公告)日：2013-08-15

申请号：US13370973

申请日：2012-02-10

申请人： Saverio Trotta

发明人： Saverio Trotta

IPC分类号： H03L7/08

CPC分类号： H03L7/06 ,  H03L2207/12

摘要： An electrical circuit including a controllable oscillator, a transmission line and a control loop. The controllable oscillator is configured to generate an oscillating signal. The transmission line is connected to an output of the oscillator, wherein the transmission line has a length which is a fraction of a wavelength of the oscillating signal. The control loop is configured to detect a difference between a first value of a signal parameter of the oscillating signal and a second value of the signal parameter of the oscillating signal having passed the transmission line. Furthermore, the control loop is configured to control the controllable oscillator in accordance with the difference.

摘要翻译： 包括可控振荡器，传输线和控制回路的电路。 可控振荡器被配置为产生振荡信号。 传输线连接到振荡器的输出，其中传输线的长度是振荡信号波长的一部分。 控制回路被配置为检测振荡信号的信号参数的第一值与经过传输线的振荡信号的信号参数的第二值之间的差值。 此外，控制环路被配置为根据差异来控制可控振荡器。

公开(公告)号：US08212715B2

公开(公告)日：2012-07-03

申请号：US12629252

申请日：2009-12-02

申请人： Armin Himmelstoss ,  Joachim Hauk ,  Elisabeth Hauk, legal representative ,  Rahel Hauk, legal representative ,  Manuel Hauk, legal representative ,  Dirk Steinbuch

发明人： Armin Himmelstoss ,  Joachim Hauk ,  Dirk Steinbuch

IPC分类号： G01S7/28

CPC分类号： H03L7/16 ,  G01S7/35 ,  G01S2013/0254 ,  H03L7/22 ,  H03L7/23 ,  H03L2207/12

摘要： A radar system includes at least two modules, each having a phase detector and a first high-frequency source and each having an antenna output and/or each having one or more antennas. At least two modules include a device for synchronization between the first high-frequency source of a first module of the at least two modules and the first high-frequency source of a second module of the at least two modules of the radar system. The phase detector has a first input for a first reference signal. The phase detector also has a second input for a first loop signal. A module for a radar system has the design of one of the modules of the radar system described above.

摘要翻译： 雷达系统包括至少两个模块，每个模块具有相位检测器和第一高频源，并且每个具有天线输出和/或每个具有一个或多个天线。 至少两个模块包括用于在至少两个模块的第一模块的第一高频源与雷达系统的至少两个模块的第二模块的第一高频源之间同步的装置。 相位检测器具有用于第一参考信号的第一输入。 相位检测器还具有用于第一回路信号的第二输入。 用于雷达系统的模块具有上述雷达系统的一个模块的设计。