公开(公告)号：US07093115B2

公开(公告)日：2006-08-15

申请号：US10326394

申请日：2002-12-19

申请人： David I. Poisner ,  Michael N. Derr ,  Darren Abramson ,  Zohar Bogin ,  Adit Tarmaster ,  William Knolla

发明人： David I. Poisner ,  Michael N. Derr ,  Darren Abramson ,  Zohar Bogin ,  Adit Tarmaster ,  William Knolla

IPC分类号： G06F15/177 ,  G06F11/22

CPC分类号： G06F9/4403

摘要： Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

摘要翻译： 本发明的实施例提供了一种用于检测存储器初始化中的中断的方法和装置。 用于指示存储器初始化是否中断的状态位是否存储在寄存器中。 基本输入/输出系统（BIOS）在初始化之前设置状态位，并在初始化后清除状态位。 状态位不能通过标准平台复位来复位。 在操作中，当系统复位或打开和初始化之前，BIOS检查状态位以检测可能的不正确的存储器初始化。 当状态位置位时，BIOS得出结论：存储器初始化尚未完成，因此可能不正确。 BIOS然后使电源循环到存储器，并且采取任何其他步骤来将存储器返回到功能状态。

公开(公告)号：US07076802B2

公开(公告)日：2006-07-11

申请号：US10334954

申请日：2002-12-31

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F1/00

CPC分类号： G06F21/71 ,  G06F1/14

摘要： Methods, apparatus and computer readable medium are described that attempt increase trust in a system time provided by a system clock. In some embodiments, a detector detects activities that may be associated with attacks against the system clock. Based upon whether the detector detects a possible attack against the system clock, the computing device may determine whether or not to trust the system time provided by the system clock.

摘要翻译： 描述了尝试增加由系统时钟提供的系统时间的信任的方法，装置和计算机可读介质。 在一些实施例中，检测器检测可能与针对系统时钟的攻击相关联的活动。 基于检测器是否检测到针对系统时钟的可能的攻击，计算设备可以确定是否信任由系统时钟提供的系统时间。

公开(公告)号：US06920553B1

公开(公告)日：2005-07-19

申请号：US09560858

申请日：2000-04-28

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F9/00 ,  G06F9/445

CPC分类号： G06F9/4401 ,  G06F11/1417

摘要： In one embodiment, a design is described for providing the BIOS instructions to a computer through the USB port. At boot-up, a USB controller checks the USB port for a bootable device containing BIOS instructions. If a bootable device is connected, the USB controller transfers the BIOS instructions through the USB port to the processor. The computer then boots-up using the USB boot instructions. If no bootable device is connected to the USB port, the computer looks to a standard BIOS EPROM for boot instructions.

摘要翻译： 在一个实施例中，描述了通过USB端口向计算机提供BIOS指令的设计。 在启动时，USB控制器检查USB端口是否包含BIOS指令的可引导设备。 如果连接了可引导设备，则USB控制器将BIOS指令通过USB端口传输到处理器。 然后，计算机使用USB启动指令启动。 如果没有可启动设备连接到USB端口，则计算机将查看标准BIOS EPROM以获取引导说明。

公开(公告)号：US06795884B2

公开(公告)日：2004-09-21

申请号：US09751272

申请日：2000-12-29

申请人： David I. Poisner ,  Louis A. Lippincott

发明人： David I. Poisner ,  Louis A. Lippincott

IPC分类号： G06F1324

CPC分类号： G06F9/3891 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3867 ,  G06F9/3885

摘要： An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

摘要翻译： 用于在用于并行存储设备接口的控制器和用于串行存储设备接口的控制器之间共享中断的设备包括：中断调节电路，其屏蔽来自并行存储设备接口的中断信号，如果没有存储设备耦合到并行存储器 设备接口 没有存储设备的并行存储设备接口中断的屏蔽耦合到并行存储设备接口，允许串行存储设备接口的控制器共享传统分配给并行存储设备接口的中断。

公开(公告)号：US06754840B2

公开(公告)日：2004-06-22

申请号：US10315156

申请日：2002-12-10

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F104

CPC分类号： G06F21/725 ,  G06F11/00 ,  G06F11/004

摘要： An over-clock deterrent mechanism of a chipset which comprises an over-clock detection circuit for detecting over-clocking of a system (processor) clock signal based on comparison of ratio of the system (processor) clock signal which is likely to be over-clocked and a fixed, stable reference clock signal which is highly unlikely to be over-clocked, and an over-clock prevention (thwarting) circuit for deterring such an over-clocking by either disabling operations of a computer system or significantly undermining key operations of a computer system.

摘要翻译： 一种芯片组的超时钟威慑机制，其包括用于基于比较可能过载的系统（处理器）时钟信号的比率来检测系统（处理器）时钟信号的超频的超时钟检测电路， 时钟和固定的稳定的参考时钟信号，这是非常不可能超时的，以及用于通过禁用计算机系统的操作来阻止这种超频的超时钟防止（阻止）电路，或显着地破坏了计算机系统的关键操作 一个电脑系统。

公开(公告)号：US06742073B1

公开(公告)日：2004-05-25

申请号：US09746162

申请日：2000-12-26

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F1340

CPC分类号： G06F13/42 ,  G06F13/4004

摘要： A technique for operating a bus controller to control N buses, each bus capable of having at least one device connected thereto, N being an integer greater than 1, includes reading a descriptor inputted to the bus controller and determining from the read descriptor whether a data transfer operation is a read operation or a write operation. The descriptor may indicate whether the device to be accessed is connected to a first bus or a second bus or alternatively, information from the descriptor may be compared with a separate list to determine if the device to be accessed is connected to the first bus or the second bus.

摘要翻译： 一种用于操作总线控制器以控制N个总线的技术，每个总线能够具有连接到其上的至少一个设备，N是大于1的整数，包括读取输入到总线控制器的描述符，并从读取的描述符确定数据 传送操作是读操作或写操作。 描述符可以指示要被访问的设备是否连接到第一总线或第二总线，或者替代地，来自描述符的信息可以与单独的列表进行比较，以确定要访问的设备是否连接到第一总线或者 第二班车。

公开(公告)号：US06374321B1

公开(公告)日：2002-04-16

申请号：US09428682

申请日：1999-10-27

申请人： Stephen S. Pawlowski ,  Darren L. Abramson ,  David I. Poisner ,  Kishore K. Mishra

发明人： Stephen S. Pawlowski ,  Darren L. Abramson ,  David I. Poisner ,  Kishore K. Mishra

IPC分类号： G06F946

摘要： In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge including ports to receive an interrupt request signal in the form of address signals and data signals. Decode logic receives at least some of the address signals and data signals and to provide a decoded signal responsive thereto. A redirection table includes a send pending bit that is set responsive to the decoded signal.

公开(公告)号：US06269443B1

公开(公告)日：2001-07-31

申请号：US09222067

申请日：1998-12-29

申请人： David I. Poisner ,  Kuljit S. Bains

发明人： David I. Poisner ,  Kuljit S. Bains

IPC分类号： G06F124

CPC分类号： G06F1/08

摘要： An apparatus for automatically selecting a processor clock frequency multiplier is disclosed. The apparatus includes a reset circuit that transmits a reset signal to a processor. When the reset signal is deasserted, the processor samples the states of various strapping signals that are provided by the apparatus. The states of the various strapping signals are determined by a clock frequency multiplier indicator circuit in the apparatus. The apparatus also includes a processor failure detection unit that determines if the processor fails to function properly after reset. If the processor failure detection unit determines that the processor is not functioning properly, the clock frequency multiplier indicator circuit indicates a smaller clock frequency multiplier and a new reset of the processor is performed by asserting the reset signal. The process is repeated until either the processor is determined to be operating properly or the clock frequency multiplier indicator circuit has indicated the smallest possible clock frequency multiplier.

摘要翻译： 公开了一种用于自动选择处理器时钟倍频器的装置。 该装置包括将复位信号发送到处理器的复位电路。 当复位信号被断言时，处理器对设备提供的各种捆扎信号的状态进行采样。 各种捆扎信号的状态由装置中的时钟倍频器指示电路确定。 该装置还包括处理器故障检测单元，其确定在复位之后处理器是否能够正常工作。 如果处理器故障检测单元确定处理器不能正常工作，则时钟倍频器指示器电路指示较小的时钟倍频器，并且通过置位复位信号来执行处理器的新复位。 重复该过程，直到处理器被确定为正常工作或时钟倍频器指示器电路已经指示尽可能小的时钟倍频器。

公开(公告)号：US5862387A

公开(公告)日：1999-01-19

申请号：US884023

申请日：1997-06-27

申请人： Neil W Songer ,  James P. Kardach ,  Sung-Soo Cho ,  Jim S. Cheng ,  Debra T. Cohen ,  John W. Horigan ,  Nader Raygani ,  Seyed Yahay Sotoudeh ,  David I. Poisner

发明人： Neil W Songer ,  James P. Kardach ,  Sung-Soo Cho ,  Jim S. Cheng ,  Debra T. Cohen ,  John W. Horigan ,  Nader Raygani ,  Seyed Yahay Sotoudeh ,  David I. Poisner

IPC分类号： G06F13/28 ,  G06F13/30 ,  G06F13/364 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/30 ,  G06F13/364

摘要： A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.

摘要翻译： 实现直接内存访问（DMA）请求传递协议的计算机系统。 计算机系统可以包括外围组件互连（PCI）总线，其包括由PCI本地总线标准指定的电接口。 PCI总线耦合到至少一个DMA代理和DMA控制器。 DMA代理使用PCI总线的电接口向DMA控制器发出DMA请求。 根据一个实施例，系统I / O控制器接收DMA请求并将它们传递到DMA控制器，DMA控制器对DMA请求进行仲裁，并将授权传回给系统I / O控制器。 系统I / O控制器使用PCI总线的电接口将授权传递给DMA代理。 相同的DMA请求传递协议可以在具有为总线的每个总线代理指定唯一请求信号线的电接口的任何总线中实现。

公开(公告)号：US5708815A

公开(公告)日：1998-01-13

申请号：US437091

申请日：1995-05-05

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F13/28 ,  G06F9/46 ,  G06F13/14

CPC分类号： G06F13/28

摘要： An apparatus and method for coordinating DMA between memory and a peripheral on a bus which does not support DMA comprises DMA emulation circuitry in the peripheral which allows the internal modules of the peripheral to share a single shared interrupt output line. An emulation device driver assists the microprocessor in determining the cause of interrupt signals received by the shared interrupt output line and how to service the interrupt.

摘要翻译： 用于在不支持DMA的总线上协调存储器和外设之间的DMA的装置和方法包括外设中的DMA仿真电路，其允许外设的内部模块共享单个共享中断输出线。 仿真设备驱动程序帮助微处理器确定共享中断输出线接收的中断信号的原因以及如何维护中断。