摘要:
An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.
摘要:
A germicidal composition comprising an aromatic dialdehyde; a medium chain linear alcohol; a surfactant; at least one enhancer selected from the group consisting of a halide salt, a carbonate and a carboxylate salt; and water, wherein the germicidal composition is a microemulsion.
摘要:
The objective of the present invention is to provide a solution for detecting timeslot conflict between Optical Network Units (ONUs) in an Optical Line Terminal (OLT). When all ONUs are deactivated and there is still any light signal in the upstream, each ONU is notified to switch off the power supply of its transmitter one by one to detect whether there is any failure ONU; when all ONUs are deactivated and there is no light signal in the upstream, the failed ONU can be located through ranging the ONUs separately. The solution can be implemented through software update, without affecting the intrinsic hardware design.
摘要:
According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.
摘要:
A method for caching of stream data is accomplished by assigning for each video segment in the system a likelihood rating of future showing and then determining for each node that contains a copy of the segment a second likelihood value that reflecting a probability that the node will be used to serve streams for the segment. The future cost value of a segment copy is then predicted and preload orders are issued to nodes for segments with the per-copy likelihood above a predefined threshold.
摘要:
An EPG service architecture incorporates multiple EPG servers connected in a cluster. An active dispatcher is associated with at least one EPG server and multiple standby dispatchers are associated with the cluster. A plurality of STBs interfaced with the EPG server cluster issue requests for EPG service for which the active dispatcher employs an affiliation table as a portion of the cache for redirecting each request to a specific one of the EPG servers affiliated with the STB issuing the request. The active dispatcher multicasts the affiliation table to the multiple standby dispatchers for synchronization.
摘要:
A system 20 includes an unbalanced device 22, a balanced device 24, and a balun (balanced-unbalanced) signal transformer 26 interposed between devices 22 and 24. The balun signal transformer 26 includes a balanced external port section 32 formed by ports 40 and 42. The balun signal transformer 26 includes a symmetric transformer 48 having a balanced port 50 formed by terminals 52 and 54. Terminal 52 is electrically interconnected with port 40, and an inductor 64 is interposed between terminal 54 and port 42. The inductor 64 shifts a phase of a signal component 72 at terminal 54 to balance substantially one hundred eighty degrees out-of-phase with a signal component 70 at terminal 52.
摘要:
Systems and methods which are adapted determine timing with respect to an orthogonal frequency division (OFD) channel, such as may be used with respect to an OFDM or OFDMA systems through reliably identifying timing of a first arriving signal path. Embodiments use deconvolution to construct the channel impulse response associated with a received signal. The first arriving path for the received signal may readily and reliably be determined using the channel impulse response information.
摘要:
The present invention provides a network search system, including: a search initiating client, configured to initiate a search request to a resource search server, and acquire network resource according to a resource feature information index returned by a resource search server; the resource search server, configured to acquire a search response client corresponding to the search initiating client according to a corresponding relation between the search response client and the search initiating client, search a resource index server corresponding to the search response client according to the search request, and return the resource feature information index to the search initiating client; the resource index server, configured to store the resource feature information index reported by the search response client. A network search method is also disclosed. By use of the present invention, it is possible to improve the instant performance of network search and the individuation of the search result.
摘要:
A method and system for buffering a clock signal is provided. The method may include self-biasing a PMOS transistor of a buffer, utilized for amplifying an in-phase/quadrature phase signal, to produce a first bias voltage at the gate of a PMOS transistor, and biasing an NMOS transistor of the buffer via a controllable current source to produce a second bias voltage at the gate of the NMOS transistor. The gain of the buffer may be controlled by varying a controllable current source coupled to a second NMOS transistor configured as a diode. Two coupling capacitors may be utilized to remove a DC component of the signal. Multiple buffers may be coupled end-to-end to increase the overall drive capability, where the channel width of the transistors within the transistors may be doubled in each successive buffer.