公开(公告)号：US06667908B2

公开(公告)日：2003-12-23

申请号：US10154417

申请日：2002-05-23

申请人： Antonino Conte ,  Oreste Concepito

发明人： Antonino Conte ,  Oreste Concepito

IPC分类号： G11C1606

CPC分类号： G11C16/28 ,  G11C16/24

摘要： A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line. First and second resistive elements are also connected between the first and second transistors and the respective bit line.

公开(公告)号：US06288960B1

公开(公告)日：2001-09-11

申请号：US09686326

申请日：2000-10-11

申请人： Antonino Conte ,  Maurizio Gaibotti ,  Tommaso Zerilli

发明人： Antonino Conte ,  Maurizio Gaibotti ,  Tommaso Zerilli

IPC分类号： G11C700

CPC分类号： G11C7/14 ,  G11C7/062

摘要： A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

摘要翻译： 用于存储器的读取放大器电路的偏置电路包括由连接在电源电压和地之间的第一对MOS晶体管形成的至少一个第一电路支路。 第一对MOS晶体管包括串联连接的P沟道二极管晶体管和N沟道晶体管，其间插入有使能晶体管。 第一个电路分支驱动电容性负载以耦合到电源电压。 偏置电路还包括用于放大在第一电路支路中流动以对电容性负载充电的参考电流的参考电流放大器电路分支。 控制电容性负载的充电电流的电路部分包括参考电流放大器电路分支和容性负载之间的反馈回路。

公开(公告)号：US08050107B2

公开(公告)日：2011-11-01

申请号：US12113721

申请日：2008-05-01

申请人： Francesco La Rosa ,  Antonino Conte

发明人： Francesco La Rosa ,  Antonino Conte

IPC分类号： G11C16/04

CPC分类号： G11C16/225 ,  G11C16/102

摘要： A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories.

摘要翻译： 一种方法将数据写入非易失性存储器。 该方法在存储器中提供包括目标页面的非易失性主存储器区域，包括辅助页面的非易失性辅助存储器区域，并且在辅助存储器区域中：包括可用于写入数据的擦除辅助页面的当前扇区， 包括辅助页面的保存扇区，包括链接到要擦除或被擦除的目标页面的数据，包括辅助页面的传送扇区，包括要传送到已擦除的目标页面的数据，以及包括要被擦除或被擦除的辅助页面的不可用扇区。 该方法可以特别地应用于闪速存储器。

公开(公告)号：US07791953B2

公开(公告)日：2010-09-07

申请号：US12113692

申请日：2008-05-01

申请人： Francesco La Rosa ,  Antonino Conte

发明人： Francesco La Rosa ,  Antonino Conte

IPC分类号： G11C16/04

CPC分类号： G11C16/225 ,  G11C16/102

摘要： A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories.

摘要翻译： 一种方法将数据写入非易失性存储器，包括包括目标位置的主存储区域和包括辅助位置的辅助存储区域。 该方法包括写擦除周期，包括：在位于主或辅助存储器区域的源位置读取初始数据集; 将要写入的数据片段插入到初始数据集中，以获得更新的数据集，部分地擦除辅助位置的第一组和由第二组辅助位置的位置指定的一组目标位置，以及写入 在第三组辅助位置的擦除辅助位置中，更新的数据集和目标位置的地址。 该方法特别适用于闪速存储器。

公开(公告)号：US07602230B2

公开(公告)日：2009-10-13

申请号：US11771157

申请日：2007-06-29

申请人： Enrico Castaldo ,  Antonino Conte ,  Gianbattista Lo Giudice

发明人： Enrico Castaldo ,  Antonino Conte ,  Gianbattista Lo Giudice

IPC分类号： H03K3/01

CPC分类号： G11C5/145 ,  G11C16/12

摘要： An integrated control circuit for a charge pump includes a first device for regulating the output voltage of the charge pump and a second device for increasing the output voltage from the charge pump with a set ramp. The integrated circuit includes means for activating said first device and providing it with a first value of a supply signal in a first period of time and for activating the second device and providing it with a second value of the supply signal that is greater than the first value in a second period of time after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value to a second value that is greater than the first value, the second value being fixed by reactivation of the first device.

摘要翻译： 用于电荷泵的集成控制电路包括用于调节电荷泵的输出电压的第一装置和用于通过设定斜坡增加来自电荷泵的输出电压的第二装置。 集成电路包括用于激活所述第一设备并且在第一时间段内向其提供电源信号的第一值并且用于激活第二设备并且向其提供大于第一设备的第二电源信号的第二值的装置 在第一次之后的第二时间段内的值以使得电荷泵的输出电压从第一值升高到大于第一值的第二值的斜坡，第二值通过重新激活固定 第一个装置

公开(公告)号：US07551041B2

公开(公告)日：2009-06-23

申请号：US11261395

申请日：2005-10-28

申请人： Antonino Conte ,  Alberto Josè Di Martino

发明人： Antonino Conte ,  Alberto Josè Di Martino

IPC分类号： H03K3/02

CPC分类号： H03K3/0231

摘要： An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.

摘要翻译： 提供了一种振荡器，其包括至少一个电容器，至少一个比较器和用于对至少一个电容器充电或放电的至少一个装置。 电容器耦合到比较器。 比较器将电容器上的电压与参考电压进行比较，并激活器件，以指示电容器的充电或放电。 振荡器还包括一个电路，用于当器件指令电容器的充电时，向比较器提供一个预置电压，以便比较器将预设电压减小的参考电压与电容器上的电压或电容器上的电压进行比较 用参考电压加到预设电压上。

公开(公告)号：US20080301357A1

公开(公告)日：2008-12-04

申请号：US12113721

申请日：2008-05-01

申请人： Francesco La Rosa ,  Antonino Conte

发明人： Francesco La Rosa ,  Antonino Conte

IPC分类号： G06F12/02

CPC分类号： G11C16/225 ,  G11C16/102

摘要： A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories.

摘要翻译： 一种方法将数据写入非易失性存储器。 该方法在存储器中提供包括目标页面的非易失性主存储器区域，包括辅助页面的非易失性辅助存储器区域，并且在辅助存储器区域中：包括可用于写入数据的已擦除辅助页面的当前扇区， 包括辅助页面的保存扇区，包括链接到要擦除或被擦除的目标页面的数据，包括辅助页面的传送扇区，包括要传送到已擦除的目标页面的数据，以及包括要被擦除或被擦除的辅助页面的不可用扇区。 该方法可以特别地应用于闪速存储器。

公开(公告)号：US20060119383A1

公开(公告)日：2006-06-08

申请号：US11063649

申请日：2005-02-22

申请人： Enrico Castaldo ,  Antonino Conte ,  Salvatore Torrisi ,  Vincenzo Sambataro

发明人： Enrico Castaldo ,  Antonino Conte ,  Salvatore Torrisi ,  Vincenzo Sambataro

IPC分类号： H03K19/003

CPC分类号： G06F1/26 ,  G11C16/30

摘要： A power management unit for a non-volatile memory device is proposed. The power management unit includes means for providing a reference voltage, resistive means for deriving a reference current from the reference voltage, means for generating a plurality of operative voltages from a power supply voltage, and means for regulating the operative voltages; in the power management unit of the invention, for each operative voltage the means for regulating includes means for deriving a scaled reference current from the reference current according to a scaling factor, further resistive means for deriving a rating voltage from the scaled reference current, means for deriving a measuring voltage from the operative voltage and the rating voltage, and means for controlling the operative voltage according to a comparison between the measuring voltage and the reference voltage.

摘要翻译： 提出了一种用于非易失性存储器件的电源管理单元。 电源管理单元包括用于提供参考电压的装置，用于从参考电压导出参考电流的电阻装置，用于从电源电压产生多个工作电压的装置，以及用于调节工作电压的装置; 在本发明的电源管理单元中，对于每个操作电压，用于调节的装置包括用于根据缩放因子从参考电流导出缩放的参考电流的装置，用于从缩放的参考电流导出额定电压的另外的电阻装置， 用于从操作电压和额定电压导出测量电压，以及用于根据测量电压和参考电压之间的比较来控制工作电压的装置。

公开(公告)号：US06774709B2

公开(公告)日：2004-08-10

申请号：US10379416

申请日：2003-03-04

申请人： Enrico Castaldo ,  Antonino Conte

发明人： Enrico Castaldo ,  Antonino Conte

IPC分类号： G05F110

CPC分类号： H02M3/073 ,  H02M2001/0032 ,  H02M2001/0041 ,  Y02B70/16

摘要： A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.

摘要翻译： 用于调节电荷泵的输出电压的电路包括连接到电荷泵的输出的调节器。 调节器包括用于分压输出电压的分压器。 滤波器具有用于接收分压输出电压的第一输入端，用于接收控制信号的第二输入端和用于提供经滤波的分压输出电压的输出端。 比较器具有用于接收分压输出电压的第一输入端，用于接收参考电压的第二输入端，用于接收经滤波的分压输出电压的第三输入端和用于根据分压输出信号的比较提供数字信号的输出端 ，参考电压和滤波后的分频输出电压。 逻辑控制电路具有用于接收时钟信号的第一输入端，用于从比较器接收数字信号的第二输入端和用于提供定时信号的输出端。 相位发生器电路具有用于接收来自逻辑控制电路的定时信号用于产生电荷泵的控制相位的输入端。

公开(公告)号：US06704233B2

公开(公告)日：2004-03-09

申请号：US10171508

申请日：2002-06-12

申请人： Antonino Conte ,  Gianbattista Lo Giudice ,  Alfredo Signorello

发明人： Antonino Conte ,  Gianbattista Lo Giudice ,  Alfredo Signorello

IPC分类号： G11C700

CPC分类号： G11C16/28

摘要： Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells including a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

摘要翻译： 用于读取和验证电可编程和可擦除非易失性存储单元的内容的感测电路，包括读出放大器，该读出放大器具有连接到要读取的单元的第一感测电路部分，并且具有用于连接到第一输入端的输出端 比较器，并且具有连接到参考电流发生器的第二参考电路部分，并且具有用于连接到所述比较器的第二输入端的输出端，其特征在于，所述第一和所述第二电路部分包括一系列第一和第二晶体管 分别连接在第一参考电压和第二电压基准之间，并且具有连接到所述第一和第二电路部分的所述输出端子的互连点。