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    Method for reducing wiring congestion in a VLSI chip design
    51.
    发明授权
    Method for reducing wiring congestion in a VLSI chip design 失效
    降低VLSI芯片设计中布线拥塞的方法

    公开(公告)号：US06958545B2

    公开(公告)日：2005-10-25

    申请号：US10755590

    申请日：2004-01-12

    申请人： Pooja M. Kotecha ,  Rama Gopal Gandham ,  Ruchir Puri ,  Louise H. Trevillyan ,  Adam P. Matheny

    发明人： Pooja M. Kotecha ,  Rama Gopal Gandham ,  Ruchir Puri ,  Louise H. Trevillyan ,  Adam P. Matheny

    IPC分类号： G06F17/50 ,  H01L23/52 ,  H01L29/40

    CPC分类号： G06F17/5077

    摘要： A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.

    摘要翻译： 一种用于校正放置和部分或全部全局路由VLSI芯片设计中的布线拥塞的系统和方法，同时避免添加新的定时或电气违规或其他设计约束。 识别全局拥挤区域以及在拥堵区域中确定终止的和未终止的电线。 该过程包括优化识别的拥塞区域，逐步重新路由受影响的网络，测试所得到的设计合法性和拥塞度量，以及提交或反转优化和重新排序。 优化还包括逻辑单元的移动以及逻辑单元结构（可能与单元移动相结合）的分解，重组或任何其它修改，以将终止的引线移动到较不拥塞的网格边缘，在单元之内或之间重新排列交换连接，或者添加 缓冲器引起馈通线的重新路由。

    Method for reducing wiring congestion in a VLSI chip design
    52.
    发明申请
    Method for reducing wiring congestion in a VLSI chip design 失效

    公开(公告)号：US20050151258A1

    公开(公告)日：2005-07-14

    申请号：US10755590

    申请日：2004-01-12

    申请人： Pooja Kotecha ,  Rama Gandham ,  Ruchir Puri ,  Louise Trevillyan ,  Adam Matheny

    发明人： Pooja Kotecha ,  Rama Gandham ,  Ruchir Puri ,  Louise Trevillyan ,  Adam Matheny

    IPC分类号： G06F17/50 ,  H01L23/52 ,  H01L29/40

    CPC分类号： G06F17/5077

    摘要： A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.

    Selecting phase assignments for candidate nodes in a logic network
    54.
    发明授权
    Selecting phase assignments for candidate nodes in a logic network 失效
    选择逻辑网络中候选节点的相位分配

    公开(公告)号：US5903467A

    公开(公告)日：1999-05-11

    申请号：US763980

    申请日：1996-12-10

    申请人： Ruchir Puri ,  Andrew Augustus Bjorksten ,  Thomas Edward Rosser

    发明人： Ruchir Puri ,  Andrew Augustus Bjorksten ,  Thomas Edward Rosser

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.

    摘要翻译： 在设计逻辑网络时，识别出定义不兼容的输出相位分配的多个节点。 选择某些不兼容的节点用于分配输出相位，使得这样选择的节点的扇出锥的NOT门被移动到网络输出。 在另一方面，该选择是响应于不兼容节点的扇入锥中的逻辑门数。

    Network flow based datapath bit slicing
    56.
    发明授权
    Network flow based datapath bit slicing 失效
    基于网络流的数据路径位分片

    公开(公告)号：US08566761B2

    公开(公告)日：2013-10-22

    申请号：US13301107

    申请日：2011-11-21

    申请人： Hua Xiang ,  Minsik Cho ,  Haoxing Ren ,  Matthew M Ziegler ,  Ruchir Puri

    发明人： Hua Xiang ,  Minsik Cho ,  Haoxing Ren ,  Matthew M Ziegler ,  Ruchir Puri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/504

    摘要： The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.

    摘要翻译： 本公开涉及一种用于确定数据路径位片的基于计算机的方法和装置。 在输入向量和输出向量之间执行第一个双向搜索以识别数据通路中的门。 然后构建包括所识别的门的网络流，并且将最小成本最大流算法应用于网络流以导出输入向量和输出向量之间的匹配比特对。 接下来，通过在输入向量中的起始位和每个匹配位对的输出向量中的结束位之间执行第二双向搜索来确定数据通路位片。

    Soft hierarchy-based physical synthesis for large-scale, high-performance circuits
    57.
    发明授权
    Soft hierarchy-based physical synthesis for large-scale, high-performance circuits 失效
    用于大规模，高性能电路的基于层次结构的物理综合

    公开(公告)号：US08516412B2

    公开(公告)日：2013-08-20

    申请号：US13222928

    申请日：2011-08-31

    申请人： Minsik Cho ,  Alvan W. Ng ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

    发明人： Minsik Cho ,  Alvan W. Ng ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/505

    摘要： In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.

    摘要翻译： 在一个实施例中，本发明是用于大规模，高性能电路的基于层次的软合成的方法和装置。 用于物理地合成集成电路的设计的方法的一个实施例包括将设计的逻辑描述编译成扁平网表，从扁平化网表中提取软层次，其中软层次结构定义了裸片上的边界， 集成电路被允许移动，并且根据软层次将集成电路的单元放置在管芯上。

    Network flow based module bottom surface metal pin assignment
    58.
    发明授权
    Network flow based module bottom surface metal pin assignment 有权
    网络流量模块底面金属引脚分配

    公开(公告)号：US08261226B1

    公开(公告)日：2012-09-04

    申请号：US13187196

    申请日：2011-07-20

    申请人： Wiren Dale Becker ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Tingdong Zhou

    发明人： Wiren Dale Becker ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Tingdong Zhou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F2217/08

    摘要： A scaled network flow graph is constructed, including a plurality of nodes and a plurality of edges. The plurality of nodes correspond to: (i) a pseudo device pin node for each pair of corresponding paired device pins; (ii) a pseudo bottom surface metal node for each pair of bottom surface metal pins on each of multiple routing layers; (iii) a source node connected to each of the pseudo device pin nodes; (iv) a sub-sink node for each pair of the paired bottom surface metal pins (each of the sub-sink nodes is connected to corresponding ones of the pseudo bottom surface metal nodes for each of the pairs of bottom surface metal pins on each of the multiple routing layers); and (v) a sink node connected to the sub-sink nodes. A capacity and a cost are assigned to each of the edges of the scaled network flow graph. A min-cost-max-flow technique is applied to the scaled network flow graph with the assigned capacities and costs to obtain an optimal flow solution. The paired bottom surface metal pins are assigned to the corresponding paired device pins, and routing connections there-between are assigned, in accordance with the optimal flow solution. A technique for use in the absence of pairing constraints is also provided, as is a pin-pairing technique.

    摘要翻译： 构建了缩放的网络流程图，包括多个节点和多个边缘。 多个节点对应于：（i）每对对应的配对设备引脚的伪器件引脚节点; （ii）在多个路由层中的每一个上的每对底表面金属销的伪底面金属节点; （iii）连接到每个伪器件引脚节点的源节点; （iv）每对成对的底表面金属销（每个子汇点中的每一个连接到每个底面表面金属节点中的每个底表面金属节点的子汇点） 的多个路由层）; 和（v）连接到子汇点节点的汇聚节点。 容量和成本被分配给缩放的网络流程图的每个边缘。 最小成本最大流技术应用于具有分配容量和成本的缩放网络流图，以获得最佳流解决方案。 配对的底面金属针脚被分配给相应的配对器件引脚，并且根据最佳流量解决方案分配其间的路由连接。 还提供了在没有配对约束的情况下使用的技术，引脚配对技术也是如此。

    Regular local clock buffer placement and latch clustering by iterative optimization
    59.
    发明授权
    Regular local clock buffer placement and latch clustering by iterative optimization 有权
    通过迭代优化进行常规本地时钟缓冲放置和锁存器聚类

    公开(公告)号：US08104014B2

    公开(公告)日：2012-01-24

    申请号：US12022951

    申请日：2008-01-30

    申请人： Ruchir Puri ,  Haifeng Qian ,  Chin Ngai Sze ,  James Warnock

    发明人： Ruchir Puri ,  Haifeng Qian ,  Chin Ngai Sze ,  James Warnock

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F2217/62

    摘要： Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.

    摘要翻译： 电源，路由和电迁移已成为现代微处理器设计中的关键问题。 在高性能设计中，时钟是功耗最大的消费者。 安排时钟组件的规律性，以便最小化时钟网络的电容可以帮助减少时钟功率，但是，由于物理放置这些组件的一些灵活性，可能会损害性能。 本发明提供了通过将锁存器的簇逻辑地分配到相应的时钟分布结构来优化设计时钟网络的技术，将时钟引脚置于有利的引脚位置，并将时钟分配结构直接放置在时钟引脚下方。 时钟分配结构可以沿着时钟条移动到有利的分配位置，并且在锁存器和时钟分配结构之间产生新的最优聚类。 优选地重复地重复这三个优化以导出时钟网络的局部最优解。

    METHOD AND APPARATUS FOR PARALLEL PROCESSING OF SEMICONDUCTOR CHIP DESIGNS
    60.
    发明申请
    METHOD AND APPARATUS FOR PARALLEL PROCESSING OF SEMICONDUCTOR CHIP DESIGNS 有权
    半导体芯片设计的并行处理方法与装置

    公开(公告)号：US20090217227A1

    公开(公告)日：2009-08-27

    申请号：US12035950

    申请日：2008-02-22

    申请人： MICHAEL W. DOTSON ,  Anthony DeGroff Drumm ,  Dazhuang J. Ma ,  Ruchir Puri ,  Louise H. Trevillyan

    发明人： MICHAEL W. DOTSON ,  Anthony DeGroff Drumm ,  Dazhuang J. Ma ,  Ruchir Puri ,  Louise H. Trevillyan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

    摘要翻译： 在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。 用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计 使用一个或多个集群，并且并行设计各个分区。