公开(公告)号：US20120044779A1

公开(公告)日：2012-02-23

申请号：US13009240

申请日：2011-01-19

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Yi-Wei Lin ,  Wei Hwang ,  Wei-Chiang Shih ,  Chia-Cheng Chen

IPC: G11C5/14

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract translation: 提供具有多个单元的随机存取存储器（RAM）。 在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。 每个电池有两个逆变器; 电源控制器有两个电源开关。 对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

公开(公告)号：US20120014171A1

公开(公告)日：2012-01-19

申请号：US12876582

申请日：2010-09-07

Applicant: Ching-Te Chuang ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

Inventor： Ching-Te Chuang ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L29/785

Abstract: The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.

Abstract translation: 本发明提供了一种基于施密特触发器的FinFET静态随机存取存储器（SRAM）单元，其是8-FinFET结构。 FinFET具有两个独立门的功能。 与之前的工作中的10-FinFET结构相比，新的SRAM单元仅使用8个FinFET。 结果，本发明的电池结构可以节省芯片面积并提高芯片密度。 此外，这种新的SRAM单元可以有效地解决6T SRAM单元在低工作电压下可能具有读出错误的常规问题。

公开(公告)号：US07876131B2

公开(公告)日：2011-01-25

申请号：US11859351

申请日：2007-09-21

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

IPC: H03K19/20 ,  H03K19/094 ,  H01L21/84

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract translation: 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

公开(公告)号：US07362606B2

公开(公告)日：2008-04-22

申请号：US11392071

申请日：2006-03-29

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract translation: 为非对称SRAM单元提供技术，例如可通过提供改进的读取稳定性和改进的写入性能和余量来提供一个或多个。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。

公开(公告)号：US07323908B2

公开(公告)日：2008-01-29

申请号：US11260571

申请日：2005-10-27

Applicant: Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

Inventor： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

IPC: H03K19/0175 ,  H03K19/094 ,  H03K3/03

CPC classification number: G01R31/31725

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract translation: 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

公开(公告)号：US07313012B2

公开(公告)日：2007-12-25

申请号：US11362613

申请日：2006-02-27

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

公开(公告)号：US07298176B2

公开(公告)日：2007-11-20

申请号：US11204401

申请日：2005-08-16

Applicant: Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

Inventor： Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

IPC: H03K19/20

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract translation: 动态逻辑门具有非对称双栅极PFET器件，用于在时钟的预充电阶段期间对动态节点进行充电。 逻辑树在时钟的评估阶段评估动态节点。 非对称双栅极PFET器件的前栅极耦合到时钟信号，而后栅极耦合到电源的地电位。 当时钟为逻辑0时，前门和后门都被偏置为ON，动态节点以最大电流充电。 在时钟关断前门的评估阶段，时钟信号转变为逻辑1。 背栅保持接通，并且非对称双栅极PFET器件作为具有足以抵抗动态节点上的泄漏的电流水平的保持器器件工作。

公开(公告)号：US20070047364A1

公开(公告)日：2007-03-01

申请号：US11216666

申请日：2005-08-31

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Hung Ngo ,  Kevin Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Hung Ngo ,  Kevin Nowka

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/412 ,  G11C11/417

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract translation: 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

公开(公告)号：US20070040621A1

公开(公告)日：2007-02-22

申请号：US11204412

申请日：2005-08-16

Applicant: Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

Inventor： Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC: H03K3/03

CPC classification number: H03K3/0315

Abstract: A ring oscillator is formed using inverting stages configured from asymmetrical dual gated FET (ADG-FET) devices. The simplest form uses an odd number of CMOS inverter stages configured with an ADG-PFET and an ADG-NFET. The front gates are used as the logic inputs and are coupled to preceeding outputs from the main ring. The back gates of the ADG-PFET devices are coupled to a first control voltage and the back gates of the ADG-NFET devices are coupled to a second control voltage that is the complement of the first control voltage referenced to an off-set voltage. Other configurations of logic inverting stages using ADG-FET devices may also be used. The control voltage is varied to modulate the current level set by the logic state at the inputs coupled to the front gates.

Abstract translation: 使用由不对称双门控FET（ADG-FET）器件配置的反相级形成环形振荡器。 最简单的形式使用由ADG-PFET和ADG-NFET配置的奇数CMOS反相器级。 前门用作逻辑输入，并连接到主环的前一个输出。 ADG-PFET器件的背栅极耦合到第一控制电压，并且ADG-NFET器件的背栅极耦合到作为基于偏移电压的第一控制电压的补码的第二控制电压。 也可以使用使用ADG-FET器件的逻辑反相级的其它配置。 改变控制电压以调制由耦合到前门的输入端处的逻辑状态设置的电流电平。

公开(公告)号：US20060290383A1

公开(公告)日：2006-12-28

申请号：US11168692

申请日：2005-06-28

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC: H03K19/096

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract translation: 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。