公开(公告)号：US06684302B2

公开(公告)日：2004-01-27

申请号：US10202030

申请日：2002-07-25

申请人： Daniel Kershaw

发明人： Daniel Kershaw

IPC分类号： G06F1200

CPC分类号： G06F12/127 ,  G06F12/0804 ,  G06F13/18

摘要： A data processing system 2 is described including a cache memory 8 and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32 within a cache controller 10 selects victim cache storage lines 28 upon a cache miss such that unlocked cache storage lines are selected in preference to locked cache storage lines, non-dirty cache storage lines are selected in preference to dirty cache storage lines, and cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM storage bank. A DRAM controller 24 is provided that continuously performs a background processing operation whereby dirty cache storage lines 28 within a cache memory 8 are written back to their respective DRAM banks 16, 18, 20, 22 when these are not busy performing other operations and when the cache storage line has a least recently used value below a certain threshold. A bus arbitration circuit 12 is provided that re-arbitrates bus master priorities in dependence upon determined latencies for respective memory access requests. As an example, if a high priority memory access request results a cache miss, with a lower priority memory access request resulting in a cache hit, then the lower priority memory access request will be re-arbitrated to be performed ahead of the normally higher priority memory access request and may be finished before that higher priority memory access request starts to return data words to a data bus 14.

摘要翻译： 描述了数据处理系统2，其包括高速缓存存储器8和多个DRAM组16,18,20,22。高速缓存控制器10内的受害者选择电路32在高速缓存未命中时选择受害者高速缓存存储线28，使得未锁定的高速缓存 存储线优先于锁定的高速缓存存储线，优先选择非脏高速缓冲存储器存储线，并且优先于缓存存储线选择需要写入非忙DRAM库的高速缓存存储线 需要写回繁忙的DRAM存储库的行。 提供DRAM控制器24，其连续执行后台处理操作，由此当高速缓存存储器8内的脏高速缓存存储线28在其不忙于执行其他操作时被写回到它们各自的DRAM存储体16,18,20,22，并且当 高速缓存存储线具有低于一定阈值的最近最近使用的值。 提供总线仲裁电路12，其根据对于各个存储器访问请求的确定的延迟重新仲裁总线主机优先级。 作为示例，如果高优先级存储器访问请求导致高速缓存未命中，则优先级较低的存储器访问请求导致高速缓存命中，则优先级较低的存储器访问请求将被重新仲裁以在正常较高优先级之前执行 存储器访问请求，并且可以在更高优先级的存储器访问请求开始将数据字返回到数据总线14之前完成。

公开(公告)号：US08997196B2

公开(公告)日：2015-03-31

申请号：US12815215

申请日：2010-06-14

申请人： Asaf Kariv ,  Oleg Ananiev ,  Eli Tovbeyn ,  Daniel Kershaw ,  Eugene (John) Neystadt

发明人： Asaf Kariv ,  Oleg Ananiev ,  Eli Tovbeyn ,  Daniel Kershaw ,  Eugene (John) Neystadt

IPC分类号： G06F7/04 ,  H04L29/06

CPC分类号： H04L63/08 ,  H04L63/102 ,  H04L2463/082

摘要： Systems, methods and apparatus for accessing at least one resource hosted by at least one server of a cloud service provider. In some embodiments, a client computer sends authentication information associated with a user of the client computer and a statement of health regarding the client computer to an access control gateway deployed in an enterprise's managed network. The access control gateway authenticates the user and determines whether the user is authorized to access the at least one resource hosted in the cloud. If the user authentication and authorization succeeds, the access control gateway requests a security token from a security token service trusted by an access control component in the cloud and forwards the security token to the client computer. The client computer sends the security token to the access component in the cloud to access the at least one resource from the at least one server.

摘要翻译： 用于访问由云服务提供商的至少一个服务器托管的至少一个资源的系统，方法和装置。 在一些实施例中，客户端计算机将与客户端计算机的用户相关联的认证信息和关于客户端计算机的健康声明发送到部署在企业的受管网络中的接入控制网关。 访问控制网关对用户进行认证，并确定用户是否被授权访问云中托管的至少一个资源。 如果用户认证和授权成功，则访问控制网关从云中的访问控制组件信任的安全令牌服务请求安全令牌，并将安全令牌转发给客户端计算机。 客户端计算机将安全令牌发送到云中的访问组件以从至少一个服务器访问该至少一个资源。

公开(公告)号：US08639975B2

公开(公告)日：2014-01-28

申请号：US12926436

申请日：2010-11-17

申请人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das ,  Daniel Kershaw

发明人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das ,  Daniel Kershaw

IPC分类号： G06F11/00

CPC分类号： G06F11/0763 ,  H03M13/09

摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.

摘要翻译： 数据处理系统2用于执行处理操作以产生结果值。 产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率 在该抗误差部分内的相同的一组操作参数的误差。 错误检测电路38检测在易错部分中产生的任何错误。 参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。 由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。

公开(公告)号：US08473819B2

公开(公告)日：2013-06-25

申请号：US12737475

申请日：2009-07-15

申请人： Daniel Kershaw ,  David Michael Bull ,  Mladen Wilder

发明人： Daniel Kershaw ,  David Michael Bull ,  Mladen Wilder

IPC分类号： H03M13/00

CPC分类号： H04L1/20 ,  H04B7/0619 ,  H04B7/0689 ,  H04B7/0691 ,  H04B17/336 ,  H04L1/0002 ,  H04L1/0025 ,  H04L25/0202

摘要： An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device. The digital performance data provides the control circuitry with additional information for use in identifying where errors in signal processing are arising, enabling an informed decision be made to modify the operation of either the transmitting device or receiving device in some way, either to reduce the occurrence of errors in the output signal or to improve the speed and/or efficiency of the transmitter and/or receiver.

摘要翻译： 描述了经由通信信道从发送设备接收数据的电子设备。 电子设备包括数字处理电路，其被布置成处理经由通信信道接收的数据以产生输出数据，布置成检测输出数据中的错误的错误检测电路以及被设置为监视由数字处理进行的数字处理的质量的监视电路 电路并产生指示数字处理的监控质量的数字性能数据。 电子设备还包括响应于错误信息的控制电路，错误信息包括由错误检测电路检测到的错误和由监控电路产生的性能数据，以修改发送设备和电子设备中的一个或两者的操作。 数字性能数据为控制电路提供附加信息，用于识别信号处理中的错误出现位置，使得能够以某种方式做出明智的决定以修改发射设备或接收设备的操作，以减少发生 的输出信号中的错误或提高发射机和/或接收机的速度和/或效率。

公开(公告)号：US07895417B2

公开(公告)日：2011-02-22

申请号：US12662734

申请日：2010-04-30

申请人： Dominic Hugo Symes ,  Daniel Kershaw ,  Mladen Wilder

发明人： Dominic Hugo Symes ,  Daniel Kershaw ,  Mladen Wilder

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： H03M13/4169 ,  G06F9/30036 ,  G06F9/345 ,  G06F9/355 ,  G06F9/3885 ,  G06F9/3887 ,  H04L1/0052 ,  H04L1/0054

摘要： A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value. The address calculation instruction and the select-and-insert instruction described above are useful when manipulating two-dimensional data arrays, and particularly so when these are two-dimensional data arrays are formed of Viterbi trellis data through which traceback operations are to be performed.

摘要翻译： 提供数据处理系统2，其包括响应于指令寄存器32内的程序指令的指令解码器34，以产生用于控制数据处理电路36的控制信号。所支持的指令包括地址计算指令，其将位置相关的输入地址值分割 在将尺寸值分配到第一部分和第二部分中时，向第一部分添加非零偏移值，将第二部分设置为值，然后将处理结果连接在第一部分和第二部分上，以形成 输出地址值。 支持的另一种类型的指令是选择和插入指令。 该指令采用第一输入值并将其移位N位位置以形成移位值，根据第一输入值从第二输入值内选择N位，然后将移位值与N位相连以形成输出 值。 上述地址计算指令和选择和插入指令在操纵二维数据阵列时非常有用，特别是当这些二维数据阵列由维特比网格数据形成时，通过该数据将执行回溯操作。

公开(公告)号：US07814302B2

公开(公告)日：2010-10-12

申请号：US12068903

申请日：2008-02-13

申请人： Dominic Hugo Symes ,  Daniel Kershaw ,  Mladen Wilder

发明人： Dominic Hugo Symes ,  Daniel Kershaw ,  Mladen Wilder

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： H03M13/4169 ,  G06F9/30036 ,  G06F9/345 ,  G06F9/355 ,  G06F9/3885 ,  G06F9/3887 ,  H04L1/0052 ,  H04L1/0054

摘要： A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value. The address calculation instruction and the select-and-insert instruction described above are useful when manipulating two-dimensional data arrays, and particularly so when these are two-dimensional data arrays are formed of Viterbi trellis data through which traceback operations are to be performed.

摘要翻译： 提供数据处理系统2，其包括响应于指令寄存器32内的程序指令的指令解码器34，以产生用于控制数据处理电路36的控制信号。所支持的指令包括地址计算指令，其将位置相关的输入地址值分割 在将尺寸值分配到第一部分和第二部分中时，向第一部分添加非零偏移值，将第二部分设置为值，然后将处理结果连接在第一部分和第二部分上，以形成 输出地址值。 支持的另一种类型的指令是选择和插入指令。 该指令采用第一输入值并将其移位N位位置以形成移位值，根据第一输入值从第二输入值内选择N位，然后将移位值与N位相连以形成输出 值。 上述地址计算指令和选择和插入指令在操纵二维数据阵列时非常有用，特别是当这些二维数据阵列由维特比网格数据形成时，通过该数据将执行回溯操作。

公开(公告)号：US20090271583A1

公开(公告)日：2009-10-29

申请号：US12149088

申请日：2008-04-25

申请人： Daniel Kershaw ,  Daren Croxford

发明人： Daniel Kershaw ,  Daren Croxford

IPC分类号： G06F12/06

CPC分类号： G06F12/1491 ,  G06F21/52

摘要： Apparatus for processing data is provided comprising processing circuitry and monitoring circuitry for monitoring write transactions and performing transaction authorisations of certain transactions in dependence upon associated memory addresses. The processing circuitry is configured to enable execution of a write instruction corresponding to a write transaction to be monitored to continue to completion whilst the monitoring circuitry is performing monitoring of the write transactions and the monitoring circuitry is arranged to cause storage of write transaction data in an intermediate storage element for those transactions for which an authorisation is required. Storage of write transaction data in an intermediate storage element enables the write transaction to be reissued in dependence upon the result of the transaction authorisation although the corresponding write instruction has already completed.

摘要翻译： 提供了用于处理数据的装置，其包括处理电路和监控电路，用于根据相关的存储器地址来监视写事务和执行某些事务的交易授权。 处理电路被配置为使得能够执行与待监视的写事务相对应的写指令以继续完成，同时监视电路正在执行对写事务的监视，并且监视电路被布置为使写事务数据存储在 需要授权的那些交易的中间存储元件。 将写入事务数据存储在中间存储元件中使得能够根据交易授权的结果重新发行写入事务，尽管相应的写入指令已经完成。

公开(公告)号：US20090248780A1

公开(公告)日：2009-10-01

申请号：US12379447

申请日：2009-02-23

申请人： Dominic H. Symes ,  Daniel Kershaw ,  Martinus C. Wezelenburg

发明人： Dominic H. Symes ,  Daniel Kershaw ,  Martinus C. Wezelenburg

IPC分类号： G06F7/52 ,  G06F5/01

CPC分类号： G06F9/3001 ,  G06F7/726

摘要： A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.

摘要翻译： 数据处理系统2包括响应多项式除法指令DIVL.PN以产生控制处理电路26执行多项式除法运算的控制信号的指令译码器22。 分母多项式由存储在寄存器中的分母值表示，假设多项式的最高度项总是具有系数“1”，使得该系数不需要存储在存储分母值的寄存器中，因此 分母多项式可以具有比存储分母值的寄存器内的位空间更高的程度。 多项式除法指令返回分别表示商多项式和余数多项式的商值和余数值。

公开(公告)号：US07587444B2

公开(公告)日：2009-09-08

申请号：US11114238

申请日：2005-04-26

申请人： Micah Rone McDaniel ,  Ann Sekli Chin ,  Daniel Kershaw

发明人： Micah Rone McDaniel ,  Ann Sekli Chin ,  Daniel Kershaw

IPC分类号： G06F7/50

CPC分类号： G06F7/509 ,  G06F7/607

摘要： A data processing apparatus for summing data values includes: a plurality of adder logic stages arranged in parallel; a control logic, in response to a request to sum two data values, to forward portions of the two data values to respective ones of the plurality of adder logic stages, each of the plurality of adder logic stages performing a carry propagate addition of the received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages for combining the intermediate sums, carries and propagate values to produce a sum of the two data values. The control logic, further in response to a request to add a third data value to the sum before the further logic has completed sum, forwards portions of the third data value to respective ones of the plurality of adder logic stages, feedbacks the intermediate sums, and selectively feedbacks a carry generated from a preceding adder logic stage. The plurality of adder logic stages perform a carry propagate addition of the fedback intermediate sums and carrys with respective portions of the third data value to generate a plurality of further intermediate sums, further carrys and further propagate values. The further logic stages combine the further intermediate sums, carries and propagate values to produce a sum of the three data values.

摘要翻译： 用于对数据值求和的数据处理装置包括：并行布置的多个加法器逻辑级; 控制逻辑，响应于求和两个数据值的请求，将所述两个数据值的部分转发到所述多个加法器逻辑级中的相应的加法器逻辑级，所述多个加法器逻辑级中的每一个执行所接收的加法器逻辑级的进位传播加法 产生中间和，传播值和进位的部分; 以及用于组合中间和的另外的逻辑级，携带和传播值以产生两个数据值的和。 所述控制逻辑还响应于在所述另外的逻辑已经完成和之前将第三数据值添加到所述和的请求，将所述第三数据值的部分转发到所述多个加法器逻辑级中的相应的加法器级， 并选择性地反馈从前一加法器逻辑级产生的进位。 多个加法器逻辑级执行反馈中间和的进位传播加法，并且与第三数据值的相应部分一起进行，以产生多个进一步的中间和，进一步承载并进一步传播值。 进一步的逻辑级组合进一步的中间和，携带和传播值以产生三个数据值的和。

公开(公告)号：US20090112955A1

公开(公告)日：2009-04-30

申请号：US12230831

申请日：2008-09-05

申请人： Daniel Kershaw ,  Mladen Wilder ,  Dominic Hugo Symes

发明人： Daniel Kershaw ,  Mladen Wilder ,  Dominic Hugo Symes

IPC分类号： G06F7/00

CPC分类号： G06F9/30014 ,  G06F9/30036

摘要： An apparatus and method is provided comprising processing circuitry, one or more registers and control circuitry. The control circuitry is configured such that it is responsive to a combined magnitude-detecting arithmetic instruction to control the processing circuitry to perform an arithmetic operation on at least one data element and further to perform a magnitude-detecting operation. The magnitude-detecting operation calculates a magnitude-indicating result providing an indication of a position of a most-significant bit of a magnitude of a result of the arithmetic operation irrespective of whether the most-significant bit position exceeds the data element width of the at least one data element.

摘要翻译： 提供了包括处理电路，一个或多个寄存器和控制电路的装置和方法。 控制电路被配置为使得其响应于组合的幅度检测算术指令以控制处理电路对至少一个数据元执行算术运算，并进一步执行幅度检测操作。 幅度检测操作计算提供算术运算结果的大小的最高有效位的位置的指示的幅度指示结果，而不管最高有效位位置是否超过at的数据元素宽度 至少一个数据元素。