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公开(公告)号：US20120124421A1
公开(公告)日：2012-05-17
申请号：US12926436
申请日：2010-11-17
IPC分类号： G06F11/07
CPC分类号： G06F11/0763 , H03M13/09
摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.
摘要翻译： 数据处理系统2用于执行处理操作以产生结果值。 产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率 在该抗误差部分内的相同的一组操作参数的误差。 错误检测电路38检测在易错部分中产生的任何错误。 参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。 由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。
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公开(公告)号：US08639975B2
公开(公告)日：2014-01-28
申请号：US12926436
申请日：2010-11-17
IPC分类号： G06F11/00
CPC分类号： G06F11/0763 , H03M13/09
摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.
摘要翻译： 数据处理系统2用于执行处理操作以产生结果值。 产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率 在该抗误差部分内的相同的一组操作参数的误差。 错误检测电路38检测在易错部分中产生的任何错误。 参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。 由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。
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公开(公告)号：US20110185262A1
公开(公告)日：2011-07-28
申请号：US12737475
申请日：2009-07-15
CPC分类号： H04L1/20 , H04B7/0619 , H04B7/0689 , H04B7/0691 , H04B17/336 , H04L1/0002 , H04L1/0025 , H04L25/0202
摘要： An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device. The digital performance data provides the control circuitry with additional information for use in identifying where errors in signal processing are arising, enabling an informed decision be made to modify the operation of either the transmitting device or receiving device in some way, either to reduce the occurrence of errors in the output signal or to improve the speed and/or efficiency of the transmitter and/or receiver.
摘要翻译： 描述了经由通信信道从发送设备接收数据的电子设备。 电子设备包括数字处理电路，其被布置成处理经由通信信道接收的数据以产生输出数据，布置成检测输出数据中的错误的错误检测电路以及被设置为监视由数字处理进行的数字处理的质量的监视电路 电路并产生指示数字处理的监控质量的数字性能数据。 电子设备还包括响应于错误信息的控制电路，错误信息包括由错误检测电路检测到的错误和由监控电路产生的性能数据，以修改发送设备和电子设备中的一个或两者的操作。 数字性能数据为控制电路提供附加信息，用于识别信号处理中的错误出现位置，使得能够以某种方式做出明智的决定以修改发射设备或接收设备的操作，以减少发生 的输出信号中的错误或提高发射机和/或接收机的速度和/或效率。
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公开(公告)号：US08473819B2
公开(公告)日：2013-06-25
申请号：US12737475
申请日：2009-07-15
IPC分类号： H03M13/00
CPC分类号： H04L1/20 , H04B7/0619 , H04B7/0689 , H04B7/0691 , H04B17/336 , H04L1/0002 , H04L1/0025 , H04L25/0202
摘要： An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device. The digital performance data provides the control circuitry with additional information for use in identifying where errors in signal processing are arising, enabling an informed decision be made to modify the operation of either the transmitting device or receiving device in some way, either to reduce the occurrence of errors in the output signal or to improve the speed and/or efficiency of the transmitter and/or receiver.
摘要翻译： 描述了经由通信信道从发送设备接收数据的电子设备。 电子设备包括数字处理电路，其被布置成处理经由通信信道接收的数据以产生输出数据，布置成检测输出数据中的错误的错误检测电路以及被设置为监视由数字处理进行的数字处理的质量的监视电路 电路并产生指示数字处理的监控质量的数字性能数据。 电子设备还包括响应于错误信息的控制电路，错误信息包括由错误检测电路检测到的错误和由监控电路产生的性能数据，以修改发送设备和电子设备中的一个或两者的操作。 数字性能数据为控制电路提供附加信息，用于识别信号处理中的错误出现位置，使得能够以某种方式做出明智的决定以修改发射设备或接收设备的操作，以减少发生 的输出信号中的错误或提高发射机和/或接收机的速度和/或效率。
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公开(公告)号：US08850041B2
公开(公告)日：2014-09-30
申请号：US12472129
申请日：2009-05-26
CPC分类号： G06F9/468
摘要： Embodiments disclosed herein extend to the use of administrative roles in a multi-tenant environment. The administrative roles define administrative tasks defining privileged operations that may be performed on the resources or data of a particular tenant. In some embodiments, the administrative tasks are a subset of administrative tasks. The administrative role also defines target objects which may be subjected to the administrative tasks. In some embodiments, the target objects are a subset of target objects. An administrator may associate a user or group of users of the particular tenant with a given administrative role. In this way, the user or group of users are delegated permission to perform the subset of administrative tasks on the subset of target objects without having to be given permission to perform all administrative tasks on all target objects.
摘要翻译： 本文公开的实施例扩展到在多租户环境中使用管理角色。 管理角色定义了可以对特定租户的资源或数据执行的特权操作的管理任务。 在一些实施例中，管理任务是管理任务的子集。 管理角色还定义了可能受到管理任务的目标对象。 在一些实施例中，目标对象是目标对象的子集。 管理员可以将特定租户的用户或一组用户与给定的管理角色相关联。 以这种方式，用户或用户组被授予在目标对象子集上执行管理任务子集的权限，而不必被授予在所有目标对象上执行所有管理任务的权限。
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6.发明授权Protecting the security of secure data sent from a central processor for processing by a further processing device 有权保护从中央处理器发送的安全数据的安全性，以便由另外的处理设备进行处理公开(公告)号：US08775824B2
公开(公告)日：2014-07-08
申请号：US12003858
申请日：2008-01-02
CPC分类号： G06F21/53 , G06F21/74 , G06F2221/2105
摘要： A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode.
摘要翻译： 一种数据处理装置，包括：用于以安全和非安全模式处理数据的数据处理器，所述数据处理器处理所述安全模式中的数据，以访问在所述非安全模式下所述数据处理器不可访问的安全数据 并且在安全操作系统的控制下执行所述安全模式中的处理数据，并且在非安全操作系统的控制下执行所述非安全模式中的数据处理; 以及用于响应于来自所述数据处理器的请求执行任务的另一处理装置，所述任务包括处理数据，其中至少一些是安全数据; 其中所述另外的处理设备响应于收到信号以暂停所述任务以启动：使用安全密钥处理所述安全数据; 以及将所述处理的安全数据存储到非安全数据存储器; 并且响应于接收到信号以恢复所述任务以启动：从所述非安全数据存储中检索所述处理的安全数据; 以及使用所述安全密钥恢复所述处理的安全数据; 其中所述安全密钥被安全地存储，使得对于在所述非安全模式中操作的其他进程是不可访问的。
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7.发明授权Data processing apparatus using implicit data storage data storage and method of implicit data storage 有权使用隐式数据存储数据存储的数据处理设备和隐式数据存储方法公开(公告)号：US08694862B2
公开(公告)日：2014-04-08
申请号：US13451728
申请日：2012-04-20
CPC分类号： H03M13/033 , G06F11/1008 , H03M13/13 , H03M13/19
摘要： A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code.
摘要翻译： 提供了一种数据处理装置，其具有错误代码产生电路，其被配置为生成与接收的数据值相关联的错误代码，使得可以通过参考错误代码了解接收的数据值中的位改变。 存储的数据值存储在数据存储中，相关的错误代码存储在错误代码存储中。 错误检查电路对存储的数据值和相关联的错误代码执行验证操作，以确定存储期间存储的数据值和相关联的错误代码中的至少一个中是否已经发生错误。 所接收的数据值包括相对于存储的数据值的至少一个附加位，并且错误检查电路被配置为通过参考所存储的数据值和相关联的错误代码来重建该至少一个附加位。
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公开(公告)号：US08255673B2
公开(公告)日：2012-08-28
申请号：US12149088
申请日：2008-04-25
申请人： Daniel Kershaw , Daren Croxford
发明人： Daniel Kershaw , Daren Croxford
IPC分类号： G06F12/00
CPC分类号： G06F12/1491 , G06F21/52
摘要： Apparatus for processing data is provided comprising processing circuitry and monitoring circuitry for monitoring write transactions and performing transaction authorizations of certain transactions in dependence upon associated memory addresses. The processing circuitry is configured to enable execution of a write instruction corresponding to a write transaction to be monitored to continue to completion while the monitoring circuitry is performing monitoring of the write transactions and the monitoring circuitry is arranged to cause storage of write transaction data in an intermediate storage element for those transactions for which an authorization is required. Storage of write transaction data in an intermediate storage element enables the write transaction to be reissued in dependence upon the result of the transaction authorization although the corresponding write instruction has already completed.
摘要翻译： 提供了用于处理数据的装置，其包括处理电路和监控电路，用于根据相关的存储器地址来监视写事务和执行某些事务的交易授权。 处理电路被配置为使得能够执行与待监视的写事务相对应的写指令以继续完成，同时监视电路正在执行对写事务的监视，并且监视电路被布置成使写事务数据存储在 需要授权的那些交易的中间存储元件。 将写入事务数据存储在中间存储元件中使得能够根据交易授权的结果重新发行写入事务，尽管相应的写入指令已经完成。
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9.发明授权Apparatus and method for performing rearrangement and arithmetic operations on data 有权对数据执行重排和算术运算的装置和方法公开(公告)号：US08255446B2
公开(公告)日：2012-08-28
申请号：US11987323
申请日：2007-11-29
IPC分类号： G06F7/38
CPC分类号： G06F7/768 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing Single Instruction Multiple Data (SIMD) processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to responsive to a combined rearrangement arithmetic instruction to control the processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation on a plurality of data elements stored in the register bank. The rearrangement operation is configurable by a size parameter derived at least in part from the register bank. The size parameter provides an indication of a number of data elements forming a rearrangement element for the purposes of the rearrangement operation. The associated method involves controlling processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation in response to a combined rearrangement arithmetic instruction and providing the scalar logic size parameter to configure the rearrangement operation. A computer program product is also provided comprising at least one combined rearrangement arithmetic instruction.
摘要翻译： 提供了一种用于对数据执行重新排列操作和算术运算的装置和方法。 数据处理装置具有用于执行单指令多数据（SIMD）处理操作和标量处理操作的处理电路，响应于程序指令来存储数据和控制电路的寄存器组，以控制处理电路执行数据处理操作。 控制电路被布置为响应于组合重排算术指令来控制处理电路对存储在寄存器组中的多个数据元素执行重新排列操作和至少一个SIMD算术运算。 重新布置操作可以由至少部分地从寄存器库导出的尺寸参数来配置。 尺寸参数提供形成用于重排操作的重新排列元件的数量元素的数量的指示。 相关联的方法涉及控制处理电路以响应于组合重排算术指令执行重排操作和至少一个SIMD算术运算，并提供标量逻辑大小参数以配置重新排列操作。 还提供了包括至少一个组合重排算术指令的计算机程序产品。
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公开(公告)号：US08010772B2
公开(公告)日：2011-08-30
申请号：US12068448
申请日：2008-02-06
CPC分类号： G06F9/322 , G06F9/30054 , G06F9/30076 , G06F9/30101 , G06F12/145 , G06F2212/1004
摘要： Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility.
摘要翻译： 存储器地址空间被划分为域，并且指令访问控制电路用于检测何时提取要执行的指令的存储器地址已经越过域边界并被改变，并且在这种情况下进行检查以确保在 新域名是允许的表单的允许指令。 允许的指令可以被布置为除指令访问控制电路之外的不操作指令，以便有助于向后兼容性。
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