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    SYNCHRONIZED DATA CHAINING USING ON-CHIP CACHE
    53.
    发明申请
    SYNCHRONIZED DATA CHAINING USING ON-CHIP CACHE 有权

    公开(公告)号：US20230005095A1

    公开(公告)日：2023-01-05

    申请号：US17943047

    申请日：2022-09-12

    Applicant: Google LLC

    Inventor： Benjamin Dodge ,  Jason Rupert Redgrave ,  Xiaoyu Ma

    IPC: G06T1/20 ,  G06F13/28 ,  G06F15/78 ,  G06T1/60

    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

    Synchronized data chaining using on-chip cache
    54.
    发明授权
    Synchronized data chaining using on-chip cache 有权

    公开(公告)号：US11443402B2

    公开(公告)日：2022-09-13

    申请号：US16609084

    申请日：2018-12-04

    Applicant: GOOGLE LLC

    Inventor： Benjamin Dodge ,  Jason Rupert Redgrave ,  Xiaoyu Ma

    IPC: G06T1/20 ,  G06T1/60 ,  G06F13/28 ,  G06F15/78

    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

    MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR
    55.
    发明申请
    MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR 有权

    公开(公告)号：US20220206796A1

    公开(公告)日：2022-06-30

    申请号：US17691615

    申请日：2022-03-10

    Applicant: Google LLC

    Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

    IPC: G06F9/30 ,  G06F7/57 ,  G06F9/38 ,  G06F15/80

    Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

    Virtual linebuffers for image signal processors
    58.
    发明授权
    Virtual linebuffers for image signal processors 有权

    公开(公告)号：US10791284B2

    公开(公告)日：2020-09-29

    申请号：US16659702

    申请日：2019-10-22

    Applicant: Google LLC

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

    IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60 ,  G06T1/20

    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

    Shift Register with Reduced Wiring Complexity
    59.
    发明申请
    Shift Register with Reduced Wiring Complexity 审中-公开

    公开(公告)号：US20200162705A1

    公开(公告)日：2020-05-21

    申请号：US16659695

    申请日：2019-10-22

    Applicant: Google LLC

    Inventor： Jason Rupert Redgrave

    IPC: H04N9/04 ,  H03K19/17736 ,  H01P5/12 ,  G11C7/10 ,  G06F15/80 ,  G06F15/173 ,  H04N5/907 ,  G11C19/38 ,  G06T1/20 ,  G11C19/00

    Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

    Macro I/O Unit for Image Processor
    60.
    发明申请
    Macro I/O Unit for Image Processor 审中-公开

    公开(公告)号：US20200160809A1

    公开(公告)日：2020-05-21

    申请号：US16685388

    申请日：2019-11-15

    Applicant: Google LLC

    Inventor： Albert Meixner ,  Neeti Desai ,  Dilan Manatunga ,  Jason Rupert Redgrave ,  William R. Mark

    IPC: G09G5/00 ,  G09G5/02 ,  G06T1/20 ,  G06F12/06 ,  G06T1/60 ,  H04N1/32

    Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.

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