公开(公告)号：US20100045912A1

公开(公告)日：2010-02-25

申请号：US12369757

申请日：2009-02-12

Applicant: Maw-Song Chen ,  Kuo-Yu Huang ,  Te-Chun Huang

Inventor： Maw-Song Chen ,  Kuo-Yu Huang ,  Te-Chun Huang

IPC: G02F1/1333 ,  G02F1/1339

CPC classification number: G02F1/13394 ,  G02F1/13454 ,  G02F2001/133388

Abstract: A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant.

Abstract translation: 驱动电路和公共电极位于第一基板的密封剂区域内，其中驱动电路包括开关装置和开关线结构。 公共电极位于第一基板的密封剂区域内。 平面层位于第一基板上，其中驱动电路的转线结构处的平面层的厚度小于其它部分的厚度。 导电层位于平面层上。 其上具有电极的第二基板设置成与第一基板相对。 液晶层位于第一基板和第二基板之间的显示区域内。 密封剂位于第一基板和第二基板之间的密封剂区域内，导电球分布在密封剂中。

公开(公告)号：US20090142923A1

公开(公告)日：2009-06-04

申请号：US12366693

申请日：2009-02-06

Applicant: Yu-Wei Liu ,  Wen-Ching Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin

Inventor： Yu-Wei Liu ,  Wen-Ching Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin

IPC: H01L21/283

CPC classification number: H01L29/4908

Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).

Abstract translation: 施加在薄膜晶体管液晶显示器（LCD）装置中的铜栅电极至​​少包括形成在玻璃基板上的图案化铜层和形成在图案化铜层上的阻挡层。 阻挡层包括氮和磷中的至少一种，或包含形式为M1M2R的合金，其中M1是钴（Co）或钼（Mo），M2是钨（W），钼（Mo），铼（Re）或钒 （V），R为硼（B）或磷（P）。

公开(公告)号：US20080003527A1

公开(公告)日：2008-01-03

申请号：US11852365

申请日：2007-09-10

Applicant: Tzeng-Guang Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin ,  Yu-Wei Liu

Inventor： Tzeng-Guang Tsai ,  Kuo-Yu Huang ,  Hui-Fen Lin ,  Yu-Wei Liu

IPC: G03C5/00 ,  B05D5/12 ,  C23C28/00

CPC classification number: H01L21/76885 ,  G02F2001/136295 ,  H01L21/76834 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0108 ,  H05K2203/0571 ,  H05K2203/0585 ,  H05K2203/0597

Abstract: The wiring line structure comprises a transparent substrate, a barrier layer, a metal layer, and a photosensitive protecting layer. The barrier layer and a metal layer are successively disposed on the transparent substrate. The photosensitive protecting layer is formed on the barrier layer and both sides of the metal layer. A method for fabricating the wiring line structure is also disclosed.

Abstract translation: 布线线结构包括透明基板，阻挡层，金属层和光敏保护层。 阻挡层和金属层依次设置在透明基板上。 感光保护层形成在阻挡层和金属层的两侧。 还公开了一种用于制造布线结构的方法。

公开(公告)号：US20070052020A1

公开(公告)日：2007-03-08

申请号：US11393742

申请日：2006-03-31

Applicant: Chi-Wen Chen ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Kuo-Yu Huang ,  Jen-Chien Peng

Inventor： Chi-Wen Chen ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Kuo-Yu Huang ,  Jen-Chien Peng

IPC: H01L27/12

CPC classification number: H01L29/66765 ,  H01L27/124 ,  H01L27/1248

Abstract: A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.

Abstract translation: 薄膜晶体管包括形成在基板上的栅电极; 覆盖栅电极的栅极绝缘层; 设置在栅极绝缘层上和栅电极上方的非晶硅（a-Si）区; 形成在a-Si区上的掺杂a-Si区; 源极和漏极金属区域分别形成在掺杂的a-Si区域和栅电极上方，并与a-Si区域隔离; 形成在所述栅极绝缘层上并覆盖所述源极，漏极和数据线（DL）金属区域的钝化层; 以及形成在钝化层上的导电层。 钝化层具有用于分别暴露源极，漏极和DL金属区域的部分表面的第一，第二和第三通孔。 第一，第二和第三通孔填充有导电层，使得DL和源极金属区域经由导电层连接。