公开(公告)号：US20120322172A1

公开(公告)日：2012-12-20

申请号：US13499288

申请日：2011-11-29

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L29/66545

摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.

摘要翻译： 本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。 根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈， 准确地不会对晶片造成任何损坏。

公开(公告)号：US08252689B2

公开(公告)日：2012-08-28

申请号：US13142736

申请日：2011-04-12

申请人： Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

发明人： Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/31155 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/78

摘要： The present invention provides a chemical-mechanical planarization method. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP.

摘要翻译： 本发明提供了一种化学机械平面化方法。 化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分 栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。 通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率 由CMP。

公开(公告)号：US20120135589A1

公开(公告)日：2012-05-31

申请号：US13142736

申请日：2011-04-12

申请人： Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

发明人： Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L21/306 ,  H01L21/304 ,  H01L21/28

CPC分类号： H01L21/31053 ,  H01L21/31155 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/78

摘要： The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP, thereby improving the within-die uniformity of the process, consequently, there will not be excess metal in the insulating layer between gates, thereby preventing device short circuit risk induced by POP CMP process.

摘要翻译： 本发明提供一种化学机械平面化方法及其制造方法。 化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分 栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。 通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率 通过CMP，从而提高了工艺的管芯内均匀性，因此在栅极之间的绝缘层中不会有过多的金属，从而防止POP CMP工艺引起的器件短路风险。

公开(公告)号：US08486805B2

公开(公告)日：2013-07-16

申请号：US13142757

申请日：2011-04-11

申请人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

发明人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

IPC分类号： H01L21/30

CPC分类号： H01L21/76898 ,  H01L21/76224 ,  H01L2924/0002

摘要： A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

摘要翻译： 提供了一种硅通孔及其形成方法。 该方法包括：提供半导体衬底，所述半导体衬底包括上表面和相对的下表面; 蚀刻半导体衬底的上表面以形成开口; 用导电材料填充开口以形成第一钉; 蚀刻半导体衬底的下表面以形成凹部，使得第一指甲暴露在凹部的底部; 用可蚀刻的导电材料填充凹部，并蚀刻可蚀刻的导电材料以形成第二钉，使得第二钉与第一钉垂直连接; 以及在所述第二钉和所述半导体衬底之间填充间隙以及所述第二钉和相邻的具有介电层的第二钉之间的间隙。 然后，本发明可以提高硅通孔的可靠性并避免空隙。

公开(公告)号：US20130059435A1

公开(公告)日：2013-03-07

申请号：US13510730

申请日：2011-11-30

申请人： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

发明人： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/51

摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

摘要翻译： 本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。 根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。 它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

公开(公告)号：US20120223431A1

公开(公告)日：2012-09-06

申请号：US13142757

申请日：2011-04-11

申请人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

发明人： Chao Zhao ,  Dapeng Chen ,  Wen Ou

IPC分类号： H01L23/48 ,  H01L21/762

CPC分类号： H01L21/76898 ,  H01L21/76224 ,  H01L2924/0002

摘要： A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

摘要翻译： 提供了一种硅通孔及其形成方法。 该方法包括：提供半导体衬底，所述半导体衬底包括上表面和相对的下表面; 蚀刻半导体衬底的上表面以形成开口; 用导电材料填充开口以形成第一钉; 蚀刻半导体衬底的下表面以形成凹部，使得第一指甲暴露在凹部的底部; 用可蚀刻的导电材料填充凹部，并蚀刻可蚀刻的导电材料以形成第二钉，使得第二钉与第一钉垂直连接; 以及在所述第二钉和所述半导体衬底之间填充间隙以及所述第二钉和相邻的具有介电层的第二钉之间的间隙。 然后，本发明可以提高硅通孔的可靠性并避免空隙。

公开(公告)号：US20140191311A1

公开(公告)日：2014-07-10

申请号：US13878655

申请日：2012-05-18

申请人： Lijun Dong ,  Dapeng Chen

发明人： Lijun Dong ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/28185 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66621

摘要： Provided is a semiconductor structure and a method for manufacturing the same. By the channel reestablishment, the tops of the source/drain regions located on both sides of the spacers are higher than bottoms of the gate stack structure and the spacers, and the source/drain regions laterally extend below the bottoms of the gate stack structure and the spacers and exceed the spacers, thereby reaching the right below of the gate stack structure. Thus, the elevated source/drain MOSFET is obtained. The semiconductor structure reduces the number of process steps, improves efficiency and decreases the cost.

摘要翻译： 提供半导体结构及其制造方法。 通过通道重建，位于间隔物两侧的源极/漏极区域的顶部高于栅极堆叠结构和间隔物的底部，并且源极/漏极区域横向延伸到栅极堆叠结构的底部以下，以及 间隔件并超过间隔件，从而到达栅极堆叠结构的正下方。 因此，获得了升高的源极/漏极MOSFET。 半导体结构减少了工艺步骤的数量，提高了效率并降低了成本。

公开(公告)号：US08563415B2

公开(公告)日：2013-10-22

申请号：US13061879

申请日：2010-06-24

申请人： Wenwu Wang ,  Shijie Chen ,  Xiaolei Wang ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Shijie Chen ,  Xiaolei Wang ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L21/3205 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517

摘要： The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented. Thereby, the EOT of the entire gate dielectric layer may be effectively controlled, and the MOS device may be continuously scaled. Meanwhile, the present invention further provides a semiconductor device obtained according to the above-mentioned method.

摘要翻译： 本发明涉及半导体器件的制造方法。 沉积金属栅电极材料后，沉积具有对氧分子具有催化功能的氧分子催化层，然后使用低温PMA退火工艺将退火气氛中的氧分子分解为更有活性的 氧原子。 这些氧原子通过金属栅极扩散到高k栅极电介质膜中，以补充高k膜中的氧空位，以便减轻高k膜中的氧空位并提高高k的质量 电影。 根据本发明，可以减轻高k栅极电介质膜的氧空位和缺陷，并且可以防止由传统的PDA高温过程引起的具有低介电常数的SiO x界面层的生长。 由此，可以有效地控制整个栅介质层的EOT，并且可以连续地缩放MOS器件。 同时，本发明还提供了根据上述方法获得的半导体器件。

公开(公告)号：US20110227163A1

公开(公告)日：2011-09-22

申请号：US13061555

申请日：2010-06-23

申请人： Wengwu Wang ,  Shijie Chen ,  Kai Han ,  Xiaolei Wang ,  Dapeng Chen

发明人： Wengwu Wang ,  Shijie Chen ,  Kai Han ,  Xiaolei Wang ,  Dapeng Chen

IPC分类号： H01L27/092

CPC分类号： H01L21/82345 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The present invention relates to a semiconductor device. Interface layers of different thickness or different materials are used in the NMOS region and the PMOS region of the semiconductor substrate, which not only effectively reduce EOT of the device, especially EOT of the PMOS device, but also increase the electron mobility of the device, especially the electron mobility of the NMOS device, thereby effectively improving the overall performance of the device.

摘要翻译： 本发明涉及一种半导体器件。 在半导体衬底的NMOS区域和PMOS区域中使用不同厚度或不同材料的界面层，其不仅有效地减少器件的EOT，特别是PMOS器件的EOT，而且还增加器件的电子迁移率， 特别是NMOS器件的电子迁移率，从而有效地提高器件的整体性能。

公开(公告)号：US08652867B2

公开(公告)日：2014-02-18

申请号：US12990037

申请日：2010-06-25

申请人： Binbin Jiao ,  Dapeng Chen

发明人： Binbin Jiao ,  Dapeng Chen

IPC分类号： H01L21/00

CPC分类号： B81C1/00158 ,  B81B2203/0353

摘要： The present invention discloses a micrometer-scale grid structure based on single crystal silicon consists of periphery frame 1 and grid zone 2. The periphery frame 1 is rectangle, and grid zone 2 has a plurality of mesh-holes 3 distributing in the plane of grid zone 2. The present invention also provides a method for manufacturing a micrometer-scale grid structure based on single crystal silicon. According to the present invention thereof, the contradiction between demand of broad deformation space for sensor and actuator and the limit of the thickness of sacrifice layer is solved. Furthermore, the special requirement of double-side transparence for some optical sensor is met.

摘要翻译： 本发明公开了一种基于单晶硅的微米尺度网格结构，由周边框架1和格栅区域2组成。外围框架1为矩形，格栅区域2具有分布在格子平面内的多个网孔3 本发明还提供了一种用于制造基于单晶硅的微米尺度网格结构的方法。 根据本发明，解决了传感器和致动器的宽变形空间需求与牺牲层厚度极限之间的矛盾。 此外，满足一些光学传感器的双面透明度的特殊要求。