公开(公告)号：US09337156B2

公开(公告)日：2016-05-10

申请号：US14248375

申请日：2014-04-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel

IPC: H01L27/092 ,  H01L27/085 ,  H01L23/00 ,  H01L21/8234 ,  H03K19/0185 ,  H01L27/112 ,  G06F21/75

CPC classification number: H01L23/576 ,  G06F21/75 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/112 ,  H01L2924/0002 ,  H03K19/018557 ,  H01L2924/00

Abstract: A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input signal has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input signal has a predetermined defined logic state.

Abstract translation: 描述了一种制造数字电路的方法，包括形成两个场效应晶体管，连接场效应晶体管，使得响应于预定输入信号的数字电路的输出信号在场效应的阈值电压时具有未定义的逻辑状态 晶体管相等并且设置场效应晶体管中的至少一个的阈值电压，使得响应于预定输入信号的数字电路的输出信号具有预定的定义的逻辑状态。

公开(公告)号：US20150381351A1

公开(公告)日：2015-12-31

申请号：US14316833

申请日：2014-06-27

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel ,  Franz Klug

IPC: H04L9/06 ,  H04L9/32 ,  G06F21/60

CPC classification number: H04L9/0618 ,  G06F21/72 ,  H04L9/003 ,  H04L9/0643 ,  H04L2209/046

Abstract: A cryptographic processor is described comprising a processing circuit configured to perform a round function of an iterated cryptographic algorithm, a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm and a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration wherein the transformation circuit is implemented using a circuit camouflage technique.

Abstract translation: 描述了一种加密处理器，其包括被配置为执行迭代密码算法的循环函数的处理电路，被配置为控制处理电路以对循环函数应用多个迭代以对消息进行处理的处理电路，该处理电路根据 迭代密码算法和变换电路，被配置为在所述多个迭代的循环函数的第一迭代之后变换所述循环函数的第二迭代的输入，并将所述变换输入作为输入提供给所述第二迭代，其中所述变换电路为 使用电路伪装技术实现。

公开(公告)号：US09195857B2

公开(公告)日：2015-11-24

申请号：US14040840

申请日：2013-09-30

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel ,  Tomaz Felicijan ,  Stefan Mangard

IPC: G06F21/71 ,  G06F21/72 ,  G06F21/44

CPC classification number: G06F21/71 ,  G06F21/445 ,  G06F21/72 ,  G06F2221/2103 ,  G06F2221/2143 ,  H04L9/004

Abstract: A computational system is configured to protect against integrity violation. The computational system includes a processing unit and a critical resource, the critical resource being controllable by the processing unit so as to be locked or unlocked. The critical resource is configured to intermittently transmit a polling value to the processing unit, and the processing unit is configured to apply a transformation onto the polling value so as to obtain a response value and send the response value back to the critical resource. The critical resource is configured to check the response value on correctness so as to obtain a check result, and subject the controllability to a dependency on the check result.

Abstract translation: 计算系统被配置为防止完整性违规。 计算系统包括处理单元和关键资源，关键资源由处理单元控制，以便被锁定或解锁。 关键资源被配置为间歇地向处理单元发送轮询值，并且处理单元被配置为将转换应用于轮询值，以便获得响应值并将响应值发送回关键资源。 配置关键资源以正确性检查响应值，以获得检查结果，并对可检测性进行检查结果的依赖。

公开(公告)号：US20150294944A1

公开(公告)日：2015-10-15

申请号：US14311378

申请日：2014-06-23

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel

IPC: H01L23/00 ,  H01L21/8234 ,  H01L27/088 ,  H03K19/003

CPC classification number: H01L23/576 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H03K3/356104 ,  H03K19/00315 ,  H03K19/094 ,  H01L2924/00

Abstract: A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input has a predetermined defined logic state.

Abstract translation: 描述了一种制造数字电路的方法，包括形成两个场效应晶体管，连接场效应晶体管，使得当场效应晶体管的阈值电压时，响应于预定输入的数字电路的输出信号具有未定义的逻辑状态 相等并且设置场效应晶体管中的至少一个的阈值电压，使得响应于预定输入的数字电路的输出信号具有预定的定义的逻辑状态。

公开(公告)号：US20150294943A1

公开(公告)日：2015-10-15

申请号：US14248375

申请日：2014-04-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel

IPC: H01L23/00 ,  H03K19/0185 ,  H01L21/8234

CPC classification number: H01L23/576 ,  G06F21/75 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/112 ,  H01L2924/0002 ,  H03K19/018557 ,  H01L2924/00

Abstract: A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input signal has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input signal has a predetermined defined logic state.

Abstract translation: 描述了一种制造数字电路的方法，包括形成两个场效应晶体管，连接场效应晶体管，使得响应于预定输入信号的数字电路的输出信号在场效应的阈值电压时具有未定义的逻辑状态 晶体管相等并且设置场效应晶体管中的至少一个的阈值电压，使得响应于预定输入信号的数字电路的输出信号具有预定的定义的逻辑状态。

公开(公告)号：US08983068B2

公开(公告)日：2015-03-17

申请号：US13786832

申请日：2013-03-06

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel ,  Stefan Mangard

IPC: H04L9/00 ,  H04L9/28 ,  H04L9/06 ,  G06F7/58 ,  G06F3/06 ,  G06F21/71 ,  G06F21/72

CPC classification number: H04L9/28 ,  G06F3/06 ,  G06F7/58 ,  G06F7/584 ,  G06F21/71 ,  G06F21/72 ,  H04L9/002 ,  H04L9/0668 ,  H04L2209/04

Abstract: An NLFSR of length k, configured to output a sequence of masked values x′i=xi+mi according to a masked recurrence x′n+k=f(x′n, . . . , x′n+k−1), the NLFSR including a nonlinear feedback function configured to compute f(x′n, . . . , x′n+k−1) so as to obtain a feedback value, a correction function configured to compute (mn, . . . , nn+k−1)+mn+k+h(mn, mn+k−1, xn, . . . , xn+k−1) to obtain a correction value c, and a corrector configured to correct the feedback value {circumflex over (x)}′n+k using the correction value c to obtain a corrected feedback value which forms x′n+k.

Abstract translation: 长度为k的NLFSR被配置为根据掩码的复现x'n + k = f（x'n，...，x'n + k-1）输出掩蔽值序列x'i = xi + mi， ，NLFSR包括被配置为计算f（x'n，...，x'n + k-1）的非线性反馈函数，以便获得反馈值，配置成计算（mn，...， nn + k-1）+ mn + k + h（mn，mn + k-1，xn，...，xn + k-1）以获得校正值c，以及校正器， 使用校正值c对（x）}'n + k进行回旋以获得形成x'n + k的校正反馈值。

公开(公告)号：US20150019878A1

公开(公告)日：2015-01-15

申请号：US13942096

申请日：2013-07-15

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F12/10 ,  G06F2212/1024 ,  G06F2212/1028 ,  Y02D10/13

Abstract: An apparatus for encrypting an input memory address to obtain an encrypted memory address is provided. The apparatus comprises an input interface for receiving the input memory address being an address of a memory. Moreover, the apparatus comprises an encryption module for encrypting the input memory address depending on a cryptographic key to obtain the encrypted memory address. The encryption module is configured to encrypt the input memory address by applying a map mapping the input memory address to the encrypted memory address, wherein the encryption module is configured to apply the map by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective.

Abstract translation: 提供了一种用于加密输入存储器地址以获得加密存储器地址的装置。 该装置包括用于接收作为存储器的地址的输入存储器地址的输入接口。 此外，该装置包括用于根据加密密钥加密输入存储器地址以获得加密的存储器地址的加密模块。 加密模块被配置为通过应用将输入存储器地址映射到加密存储器地址的映射来加密输入存储器地址，其中加密模块被配置为通过使用密码密钥进行乘法和模运算来应用映射， 模数运算的除数，使得地图是双射的。

公开(公告)号：US20140254792A1

公开(公告)日：2014-09-11

申请号：US13786832

申请日：2013-03-06

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel ,  Stefan Mangard

IPC: H04L9/28

CPC classification number: H04L9/28 ,  G06F3/06 ,  G06F7/58 ,  G06F7/584 ,  G06F21/71 ,  G06F21/72 ,  H04L9/002 ,  H04L9/0668 ,  H04L2209/04

Abstract: An NLFSR of length k, configured to output a sequence of masked values xi′=xi+mi according to a masked recurrence xn+k′=f(xn′, . . . , xn+k−1′), the NLFSR including a nonlinear feedback function configured to compute f(xn′, . . , , xn+k−1′) so as to obtain a feedback value, a correction function configured to compute (mn, . . . , nn+k−1)+mn+k+h(mn, mn+l−1, xn, . . . , xn+k−1) to obtain a correction value c, and a corrector configured to correct the feedback value {circumflex over (x)}n+k′ using the correction value c to obtain a corrected feedback value which forms xn+k′.

Abstract translation: 根据掩蔽的复现xn + k'= f（xn'，...，xn + k-1'），设置长度为k的NLFSR，其包括以下步骤：输出掩蔽值序列xi'= xi + mi，NLFSR包括 非线性反馈函数，被配置为计算f（xn'，...，xn + k-1'）以获得反馈值，配置为计算（mn，...，nn + k-1） + mn + k + h（mn，mn + l-1，xn，...，xn + k-1）以获得校正值c，以及校正器，被配置为校正反馈值{ n + k'使用校正值c来获得形成xn + k'的校正反馈值。

公开(公告)号：US20130176053A1

公开(公告)日：2013-07-11

申请号：US13775789

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

IPC: H03K19/20

CPC classification number: H03K19/20 ,  G11C13/0004 ,  H01L27/24

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Abstract translation: 集成电路具有一个或多个逻辑门和控制电路。 控制电路具有耦合到逻辑门的一个或多个控制元件。 控制电路控制一个或多个逻辑门的状态。