公开(公告)号：US20200067987A1

公开(公告)日：2020-02-27

申请号：US16546803

申请日：2019-08-21

Applicant: Infineon Technologies AG

Inventor： Josef Haid ,  Stefan Rueping

IPC: H04L29/06

Abstract: A device includes a root of trust and a controller to perform a device function of the device using the root of trust. The root of trust is designed to control and/or observe the controller at least partially for the performance of the device function.

公开(公告)号：US09356604B2

公开(公告)日：2016-05-31

申请号：US13775789

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

IPC: H03K19/20 ,  G11C13/00 ,  H01L27/24

CPC classification number: H03K19/20 ,  G11C13/0004 ,  H01L27/24

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Abstract translation: 集成电路具有一个或多个逻辑门和控制电路。 控制电路具有耦合到逻辑门的一个或多个控制元件。 控制电路控制一个或多个逻辑门的状态。

公开(公告)号：US20130176053A1

公开(公告)日：2013-07-11

申请号：US13775789

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

IPC: H03K19/20

CPC classification number: H03K19/20 ,  G11C13/0004 ,  H01L27/24

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Abstract translation: 集成电路具有一个或多个逻辑门和控制电路。 控制电路具有耦合到逻辑门的一个或多个控制元件。 控制电路控制一个或多个逻辑门的状态。

公开(公告)号：US11552998B2

公开(公告)日：2023-01-10

申请号：US16546803

申请日：2019-08-21

Applicant: Infineon Technologies AG

Inventor： Josef Haid ,  Stefan Rueping

IPC: H04L9/40

Abstract: A device includes a root of trust and a controller to perform a device function of the device using the root of trust. The root of trust is designed to control and/or observe the controller at least partially for the performance of the device function.

公开(公告)号：US10261899B2

公开(公告)日：2019-04-16

申请号：US14475651

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Stefan Rueping

IPC: G06F12/02

Abstract: A method for data processing including mapping between a logical address and a physical address of a memory, wherein the memory comprises several pages, wherein a group of pages comprises at least one page that comprises at least two portions, and wherein the at least two portions of each page of the group are not part of a single-page logical address space.