公开(公告)号：US20190034340A1

公开(公告)日：2019-01-31

申请号：US15855104

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Francesc Guim Bernat ,  Daniel Rivas Barragan ,  Suraj Prabhakaran

IPC: G06F12/0831 ,  G06F17/30 ,  G06F13/16

Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.

公开(公告)号：US10084724B2

公开(公告)日：2018-09-25

申请号：US15260626

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan

IPC: H04L12/933 ,  H04L12/931 ,  G06F3/06 ,  H04L29/08 ,  G06F12/084

CPC classification number: H04L49/103 ,  G06F3/067 ,  G06F12/084 ,  H04L29/08135 ,  H04L49/355 ,  H04L67/1097

Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a computing node that includes a host fabric interface (HFI) usable to communicate with network computing devices of the fabric architecture. The HFI is configured to associate an object with a transaction identifier generated by the HFI for a corresponding transactional synchronization session managed by the HFI of the computing node. Additionally, the HFI is configured to store received data associated with received write transaction that include the transaction identifier in a local buffer of the HFI. Upon receiving a transactional synchronization session termination request, the HFI is configured to initiate a write of the data stored in the local buffer of the HFI to one of the one or more data storage devices of the computing node. Other embodiments are described herein.

公开(公告)号：US20180006951A1

公开(公告)日：2018-01-04

申请号：US15201394

申请日：2016-07-02

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: H04L12/803 ,  H04L29/08 ,  H04L12/26

CPC classification number: H04L43/08 ,  G06F9/505 ,  H04L43/0817 ,  H04L43/0852 ,  H04L43/0888 ,  H04L43/0894 ,  H04L47/822 ,  H04L49/505 ,  H04L67/1002 ,  H04L67/1023

Abstract: Examples may include techniques to distribute queries in a fabric of nodes configured to process the queries. A load balancing switch coupled to the nodes can receive indications of resource metrics from the nodes and can schedule and distribute the queries based on the resource metrics and network metrics identified by the switch. The switch can include programmable circuitry to receive selected resource metrics and identify selected network metrics and to distribute queries to nodes based on the metrics and distribution logic.