公开(公告)号：US12120175B2

公开(公告)日：2024-10-15

申请号：US17688695

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Thomas Willhalm ,  Karthik Kumar ,  Timothy Verrall

IPC: H04L67/1008 ,  H04L67/00 ,  H04L67/10 ,  H04L67/1021 ,  H04L67/59 ,  H04L67/61 ,  H04L67/63

CPC classification number: H04L67/1008 ,  H04L67/10 ,  H04L67/1021 ,  H04L67/34 ,  H04L67/59 ,  H04L67/61 ,  H04L67/63

Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.

公开(公告)号：US20240256685A1

公开(公告)日：2024-08-01

申请号：US18629695

申请日：2024-04-08

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F21/60 ,  G06F3/06 ,  H04W12/50

CPC classification number: G06F21/606 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  H04W12/50

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. An embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. Other embodiments are disclosed and claimed.

公开(公告)号：US11983437B2

公开(公告)日：2024-05-14

申请号：US16882833

申请日：2020-05-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Donald Faw ,  Thomas Willhalm

IPC: G06F3/06 ,  G06F1/30 ,  G06F13/40

CPC classification number: G06F3/0659 ,  G06F1/30 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/4022

Abstract: In one embodiment, an apparatus includes: a first queue to store requests that are guaranteed to be delivered to a persistent memory; a second queue to store requests that are not guaranteed to be delivered to the persistent memory; a control circuit to receive the requests and to direct the requests to the first queue or the second queue; and an egress circuit coupled to the first queue to deliver the requests stored in the first queue to the persistent memory even when a power failure occurs. Other embodiments are described and claimed.

公开(公告)号：US20220263891A1

公开(公告)日：2022-08-18

申请号：US17688695

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Thomas Willhalm ,  Karthik Kumar ,  Timothy Verrall

IPC: H04L67/1008 ,  H04L67/1021 ,  H04L67/10 ,  H04L67/00 ,  H04L67/59 ,  H04L67/61 ,  H04L67/63

Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.

公开(公告)号：US11196837B2

公开(公告)日：2021-12-07

申请号：US16369384

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Petar Torre ,  Ned Smith ,  Brinda Ganesh ,  Evan Custodio ,  Suraj Prabhakaran

IPC: H04L12/911 ,  H04L29/08 ,  H04L12/66

Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.

公开(公告)号：US11115497B2

公开(公告)日：2021-09-07

申请号：US16829814

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Slawomir Putyrski ,  Susanne M. Balle ,  Thomas Willhalm ,  Karthik Kumar

IPC: H04L29/08 ,  H04L12/911

Abstract: Technologies for providing advanced resource management in a disaggregated environment include a compute device. The compute device includes circuitry to obtain a workload to be executed by a set of resources in a disaggregated system, query a sled in the disaggregated system to identify an estimated time to complete execution of a portion of the workload to be accelerated using a kernel, and assign, in response to a determination that the estimated time to complete execution of the portion of the workload satisfies a target quality of service associated with the workload, the portion of the workload to the sled for acceleration.

公开(公告)号：US10969975B2

公开(公告)日：2021-04-06

申请号：US16529533

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  John Chun Kwok Leung ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F3/06 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system comprising a computing fabric with a plurality of different disaggregated computing hardware resources having respective hardware characteristics. A resource manager has access to the respective hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources with respective hardware characteristics meeting requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule the application using the assembled composite computing node.

公开(公告)号：US10951516B2

公开(公告)日：2021-03-16

申请号：US16291541

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Brian J. Slechta

IPC: H04L12/725 ,  H04L12/803 ,  H04L12/933 ,  H04L12/825 ,  H04L12/931

Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

公开(公告)号：US10944689B2

公开(公告)日：2021-03-09

申请号：US16024465

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Mark A. Schmisseur ,  Timothy Verrall

IPC: G06F15/173 ,  H04L12/919 ,  H04L12/911 ,  G06F9/50 ,  G06N20/00

Abstract: There is disclosed in one example a communication apparatus, including: a telemetry interface; a management interface; and an edge gateway configured to: identify diverted traffic, wherein the diverted traffic includes traffic to be serviced by an edge microcloud configured to provide a plurality of services; receive telemetry via the telemetry interface; use the telemetry to anticipate a future per-service demand within the edge microcloud; compute a scale for a resource to meet the future per-service demand; and operate the management interface to instruct the edge microcloud to perform the scale before the future per-service demand occurs.

公开(公告)号：US10782969B2

公开(公告)日：2020-09-22

申请号：US15979223

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Thomas Willhalm

IPC: G06F9/30 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache line write back instruction is to indicate a source packed memory indices operand that is to include a plurality of memory indices. The processor also includes a cache coherency system coupled with the packed data registers and the decode unit. The cache coherency system, in response to the vector cache line write back instruction, to cause, any dirty cache lines, in any caches in a coherency domain, which are to have stored therein data for any of a plurality of memory addresses that are to be indicated by any of the memory indices of the source packed memory indices operand, to be written back toward one or more memories. Other processors, methods, and systems are also disclosed.