公开(公告)号：US20190319799A1

公开(公告)日：2019-10-17

申请号：US16455921

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08 ,  G06F9/38

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US12289161B2

公开(公告)日：2025-04-29

申请号：US17829042

申请日：2022-05-31

Applicant: INTEL CORPORATION

Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Manoj Sastry ,  Marcio Juliato ,  Shabbir Ahmed ,  Qian Wang

IPC: H04J3/06

Abstract: Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information. Other embodiments are described and claimed.

公开(公告)号：US12250233B2

公开(公告)日：2025-03-11

申请号：US18105580

申请日：2023-02-03

Applicant: INTEL CORPORATION

Inventor： Marcio Juliato ,  Javier Perez-Ramirez ,  Manoj Sastry ,  Dave Cavalcanti ,  Christopher Gutierrez ,  Vuk Lesi ,  Shabbir Ahmed

IPC: H04L9/40

Abstract: Techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. Embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. Embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. Other embodiments are described and claimed.

公开(公告)号：US12218813B2

公开(公告)日：2025-02-04

申请号：US18215936

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Javier Perez-Ramirez ,  Mikhail Galeev ,  Manoj Sastry ,  Dave Cavalcanti ,  Christopher Gutierrez ,  Shabbir Ahmed ,  Vuk Lesi

IPC: H04L43/0817 ,  H04L9/40 ,  H04L43/067

Abstract: Techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. Embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. Embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. Other embodiments are described and claimed.

公开(公告)号：US20250007738A1

公开(公告)日：2025-01-02

申请号：US18215951

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Christopher Gutierrez ,  Marcio Juliato ,  Manoj Sastry ,  Vuk Lesi ,  Shabbir Ahmed

IPC: H04L9/40 ,  H04L9/32

Abstract: Techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. Embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. Embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. Other embodiments are described and claimed.

公开(公告)号：US20240267212A1

公开(公告)日：2024-08-08

申请号：US18164487

申请日：2023-02-03

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/08 ,  H04L9/30

CPC classification number: H04L9/0869 ,  H04L9/3093

Abstract: Key encapsulation implemented by random sample generator circuitry to generate a plurality of pseudorandom bitstreams; polynomial multiplier circuitry to multiply a plurality of polynomial coefficients; and a controller to power off the polynomial multiplier circuitry and power on the random sample generator circuitry to generate the plurality of pseudorandom bitstreams, and power off the random sample generator circuitry and power on the polynomial multiplier circuitry to multiple the plurality of polynomial coefficients.

公开(公告)号：US12054119B2

公开(公告)日：2024-08-06

申请号：US16994147

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Shabbir Ahmed ,  Marcio Juliato ,  Christopher Gutierrez ,  Qian Wang ,  Vuk Lesi ,  Manoj Sastry

IPC: B60R25/30 ,  B60R25/104 ,  B60R25/24 ,  G06F21/44 ,  H04L9/40

CPC classification number: B60R25/30 ,  B60R25/104 ,  B60R25/24 ,  G06F21/44 ,  H04L63/1416

Abstract: Systems, apparatuses, and methods to identify an electronic control unit transmitting a message on a communication bus, such as an in-vehicle network bus, are provided. ECUs transmit messages by manipulating voltage on conductive lines of the bus. Observation circuitry can observe voltage transitions associated with the transmission at a point on the in-vehicle network bus. A domain bitmap can be generated from the observed voltage transitions. ECUs can be identified and/or fingerprinted based on the domain bitmaps.

公开(公告)号：US12034736B2

公开(公告)日：2024-07-09

申请号：US17484330

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Javier Perez-Ramirez ,  Mikhail Galeev ,  Christopher Gutierrez ,  Dave Cavalcanti ,  Manoj Sastry ,  Vuk Lesi

IPC: H04L29/06 ,  H04L9/06 ,  H04L9/40 ,  H04L69/22 ,  H04L69/28

CPC classification number: H04L63/105 ,  H04L9/0656 ,  H04L63/1483 ,  H04L69/22 ,  H04L69/28

Abstract: Systems and methods to detect attacks on the clocks of devices in time sensitive networks are described. Particularly, the disclosed systems and methods provide detection and mitigation of timing synchronization attacks based on pseudo-random numbers generated and used to select and authenticate timing of transmission of messages in protected transmission windows.

公开(公告)号：US11995184B2

公开(公告)日：2024-05-28

申请号：US17484870

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Manoj Sastry

IPC: G06F21/55 ,  G06F7/72 ,  G06F21/64 ,  G06F21/75 ,  H04L9/00 ,  H04L9/30 ,  H04L9/32

CPC classification number: G06F21/556 ,  G06F7/724 ,  G06F21/64 ,  G06F21/75 ,  H04L9/003 ,  H04L9/3093 ,  H04L9/3247 ,  G06F2207/7223

Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

公开(公告)号：US11995183B2

公开(公告)日：2024-05-28

申请号：US17357885

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Vuk Lesi ,  Manoj Sastry ,  Qian Wang

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: Systems, apparatuses, and methods to response to detected attacks in an autonomous system based on context of the autonomous system are described. In particular, the disclosure provides an intrusion detection system receiving contexts and contracts dictating particular response guide rails from a higher level components or stack on the autonomous system. The intrusion detection system is arranged to respond to attacks according to the contract without intervention by the higher level components or stack.