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    Compute near memory convolution accelerator
    53.
    发明授权
    Compute near memory convolution accelerator 有权

    公开(公告)号：US11726950B2

    公开(公告)日：2023-08-15

    申请号：US16586975

    申请日：2019-09-28

    Applicant: Intel Corporation

    Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram Krishnamurthy

    IPC: G06F15/80 ,  G06F17/15 ,  G06N3/063

    CPC classification number: G06F15/8046 ,  G06F17/153 ,  G06N3/063

    Abstract: A compute near memory (CNM) convolution accelerator enables a convolutional neural network (CNN) to use dedicated acceleration to achieve efficient in-place convolution operations with less impact on memory and energy consumption. A 2D convolution operation is reformulated as 1D row-wise convolution. The 1D row-wise convolution enables the CNM convolution accelerator to process input activations row-by-row, while using the weights one-by-one. Lightweight access circuits provide the ability to stream both weights and input rows as vectors to MAC units, which in turn enables modules of the CNM convolution accelerator to implement convolution for both [1×1] and chosen [n×n] sized filters.

    Weight prefetch for in-memory neural network execution
    55.
    发明授权
    Weight prefetch for in-memory neural network execution 有权

    公开(公告)号：US11347994B2

    公开(公告)日：2022-05-31

    申请号：US16160466

    申请日：2018-10-15

    Applicant: Intel Corporation

    Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

    IPC: G06F3/06 ,  G06N3/04 ,  G06F12/0875 ,  G06N3/063

    Abstract: The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES
    57.
    发明申请
    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES 有权

    公开(公告)号：US20220108039A1

    公开(公告)日：2022-04-07

    申请号：US17551961

    申请日：2021-12-15

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

    IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

    Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

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