公开(公告)号：US20060068737A1

公开(公告)日：2006-03-30

申请号：US11227909

申请日：2005-09-16

申请人： Yido Koo ,  Youngho Ahn ,  Eunseok Song ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Yido Koo ,  Youngho Ahn ,  Eunseok Song ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H04B1/40 ,  H04B7/00 ,  H03D3/24 ,  H04B1/06

CPC分类号： H03L7/0895 ,  H03L7/1976

摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

公开(公告)号：US06993109B2

公开(公告)日：2006-01-31

申请号：US10231312

申请日：2002-08-30

申请人： Kyeongho Lee ,  Joonbae Park

发明人： Kyeongho Lee ,  Joonbae Park

IPC分类号： H03D3/24

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/23 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067

摘要： A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

公开(公告)号：US20060003720A1

公开(公告)日：2006-01-05

申请号：US11057414

申请日：2005-02-15

申请人： Kang Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Kang Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H04B1/40 ,  H04B1/06 ,  H04B7/00

CPC分类号： H03L7/085 ,  H03L7/099 ,  H03L7/1976 ,  H03L7/199

摘要： An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal. In one embodiment, coarse tuning and lead-lag detection is performed more accurately to allow the size of the varactors to become significantly reduced compared with other circuits which have been proposed.

公开(公告)号：US06930560B2

公开(公告)日：2005-08-16

申请号：US10183974

申请日：2002-06-25

申请人： Kyeongho Lee ,  Deog-kyoon Jeong

发明人： Kyeongho Lee ,  Deog-kyoon Jeong

IPC分类号： H03K5/26 ,  H03L7/089 ,  H03L7/00

CPC分类号： H03L7/0891

摘要： A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.

摘要翻译： 锁相环包括电荷泵，压控振荡器（VCO）和相位频率检测器。 相位频率检测器具有动态逻辑结构。 相位频率检测器产生用于引导电荷泵的上升和下降信号以向VCO提供电压信号以改变VCO时钟的频率。 上升和下降信号之间的差异表示参考时钟信号和VCO时钟之间的相位差。 相位频率检测器包括分别产生上下信号的上下信号发生器。

公开(公告)号：US06850748B2

公开(公告)日：2005-02-01

申请号：US10207986

申请日：2002-07-31

申请人： Eunseok Song ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Eunseok Song ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H04B1/28 ,  H04B1/52 ,  H04B1/00

CPC分类号： H04B1/28 ,  H04B1/525

摘要： A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider that divides an input signal frequency by a predetermined value to produce an output signal frequency; and a frequency mixer that mixes the output signal frequency with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency and the carrier signal frequency. The predetermined value and the input signal frequency are selected such that the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency. The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.

摘要翻译： 公开了一种在射频前端提供频率转换的方法和装置，包括将输入信号频率除以预定值以产生输出信号频率的分频器; 以及混频器，其将输出信号频率与载波信号频率进行混合，以产生基本上等于输出信号频率和载波信号频率之差的转换信号频率。 选择预定值和输入信号频率使得载波信号频率基本上不等于输出信号频率的整数倍。 该方法和装置可用于包括无线通信系统和无线LAN系统的无线通信接收机。

公开(公告)号：US06781424B2

公开(公告)日：2004-08-24

申请号：US10253534

申请日：2002-09-25

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。

公开(公告)号：US06512408B2

公开(公告)日：2003-01-28

申请号：US09985897

申请日：2001-11-06

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F744

CPC分类号： H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

公开(公告)号：US06483355B1

公开(公告)日：2002-11-19

申请号：US09709637

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。

公开(公告)号：US06326826B1

公开(公告)日：2001-12-04

申请号：US09574571

申请日：2000-05-17

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L700

CPC分类号： H03L7/087 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/10 ,  H03L2207/14

摘要： A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.

摘要翻译： 描述了包括频率检测逻辑和相位检测器的延迟锁定环（DLL），其具有与常规电荷泵锁相环一样​​宽的操作范围。 频率检测器逻辑计算在参考时钟的一个周期期间从参考时钟产生的多相时钟的上升沿的数量。 环路滤波器用于调整每个多相时钟的频率，直到通过比较上升沿的数量获得频率锁定为止。 在频率锁定之后，相位检测逻辑用于微调剩余的相位误差。

公开(公告)号：US6157263A

公开(公告)日：2000-12-05

申请号：US98266

申请日：1998-06-16

申请人： Kyeongho Lee ,  Deog-kyoon Jeong

发明人： Kyeongho Lee ,  Deog-kyoon Jeong

IPC分类号： H03K5/26 ,  H03L7/089 ,  H03L7/00

CPC分类号： H03L7/0891

摘要： A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal. A third p FET has a gate coupled to the drain of the second p FET. A second n FET has a source coupled to the drain of the third p FET for providing the up signal, and has a gate for receiving the reference clock signal. A third n FET has a source coupled to the drain of the second n FET and has a gate coupled to the gate of the third p FET. The down signal generator includes a fourth p FET having a gate for receiving the set signal. A fifth p FET has a source coupled to the drain of the fourth p FET and has a gate for receiving a VCO clock signal. A fourth n FET has a source coupled to the drain of the fifth n FET and has a gate for receiving the set signal. A sixth p FET has a gate coupled to the drain of the fifth p FET. A fifth n FET has a source coupled to the drain of the sixth p FET and has a gate for receiving the VCO clock signal. A sixth n FET has a source coupled to the drain of the fifth n FET for providing the down signal, and has a gate coupled to the gate of the sixth p FET. A reset circuit, such as a NAND gate, has a first input coupled to the drain of the third p FET, has a second input coupled to the drain of the sixth p FET, and has an output for generating the set signal.