公开(公告)号：US07035351B1

公开(公告)日：2006-04-25

申请号：US09705696

申请日：2000-11-06

申请人： Joonbae Park ,  Wonchan Kim ,  Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Joonbae Park ,  Wonchan Kim ,  Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03D3/18

CPC分类号： H04B1/30 ,  H03F3/211 ,  H03F2200/294 ,  H03F2200/372

摘要： A DC offset cancelling circuit with multiple feedback loops suppresses DC offset voltages within an automatic gain control loop apparatus. The apparatus includes a plurality of gain stages connected in series that receive and amplify an input RF signal. Each gain stage includes a corresponding feedback loop to filter the DC offset voltage accumulated in the respective gain stage.

摘要翻译： 具有多个反馈环路的DC偏移消除电路抑制自动增益控制环路装置内的DC偏移电压。 该装置包括串联连接的多个增益级，其接收和放大输入RF信号。 每个增益级包括相应的反馈回路以对累积在相应增益级中的DC偏移电压进行滤波。

公开(公告)号：US06781424B2

公开(公告)日：2004-08-24

申请号：US10253534

申请日：2002-09-25

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。

公开(公告)号：US06483355B1

公开(公告)日：2002-11-19

申请号：US09709637

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong ,  Joonbae Park ,  Wonchan Kim

IPC分类号： H04B118

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/18 ,  H04B1/28 ,  H04B1/40

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统可以包括接收/发射RF信号的天线，产生具有与载波频率不同的频率的多相时钟信号的PLL和具有载波频率的参考信号， 混频器将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合以输出相对于载波频率降低的频率的信号;将所选频道信号放大到所需动态电平的两级放大， 以及用于将来自混合单元的RF信号转换为数字信号的A / D转换单元。 即使相邻信道信号由具有较大幅度或功率的解调混频器输出，两级放大可以提供所选择的信道信号足够的增益。

公开(公告)号：US06313688B1

公开(公告)日：2001-11-06

申请号：US09709315

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F744

CPC分类号： H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

摘要翻译： 根据本发明的混合器结构及其使用方法包括多相混合器。 VCO包括多个差分延迟单元，以输出多个多相时钟信号。 多相混频器可以包括负载电路，开关电路，降噪电路和输入电路。 开关电路被耦合以接收多个多相时钟信号，并且包括分别耦合到负载电路的第一开关阵列和第二开关阵列。 耦合到开关电路的降噪电路可以包括响应偏置电压的晶体管。 输入电路包括接收输入信号的晶体管。 第一开关阵列包括耦合在第一输出端子和第二节点之间的第一多个开关，并且第二开关阵列包括耦合在第二输出端子和第二节点之间的第二多个开关。 优选地，多个开关中的每一个包括两对串联连接的晶体管，其中串联连接的晶体管并联耦合以为两个输入端口中的每一个提供对称电连接。 混频器和使用它的方法可以是接收RF输入信号的单或双平衡混频器。

公开(公告)号：US5815041A

公开(公告)日：1998-09-29

申请号：US631420

申请日：1996-04-12

申请人： Kyeongho Lee ,  Deog-kyoon Jeong

发明人： Kyeongho Lee ,  Deog-kyoon Jeong

IPC分类号： H03K5/26 ,  H03L7/089 ,  H03K5/13

CPC分类号： H03L7/0891

摘要： A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal. A third p FET has a gate coupled to the drain of the second p FET. A second n FET has a source coupled to the drain of the third p FET for providing the up signal, and has a gate for receiving the reference clock signal. A third n FET has a source coupled to the drain of the second n FET and has a gate coupled to the gate of the third p FET. The down signal generator includes a fourth p FET having a gate for receiving the set signal. A fifth p FET has a source coupled to the drain of the fourth p FET and has a gate for receiving a VCO clock signal. A fourth n FET has a source coupled to the drain of the fifth n FET and has a gate for receiving the set signal. A sixth p FET has a gate coupled to the drain of the fifth p FET. A fifth n FET has a source coupled to the drain of the sixth p FET and has a gate for receiving the VCO clock signal. A sixth n FET has a source coupled to the drain of the fifth n FET for providing the down signal, and has a gate coupled to the gate of the sixth p FET. A reset circuit, such as a NAND gate, has a first input coupled to the drain of the third p PET, has a second input coupled to the drain of the sixth p FET, and has an output for generating the set signal.

公开(公告)号：US06462624B1

公开(公告)日：2002-10-08

申请号：US09693516

申请日：2000-10-20

申请人： Kyeongho Lee ,  Deog-kyoon Jeong

发明人： Kyeongho Lee ,  Deog-kyoon Jeong

IPC分类号： H03L700

CPC分类号： H03L7/0891

摘要： A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal. A third p FET has a gate coupled to the drain of the second p FET. A second n FET has a source coupled to the drain of the third p FET for providing the up signal, and has a gate for receiving the reference clock signal. A third n FET has a source coupled to the drain of the second n FET and has a gate coupled to the gate of the third p FET. The down signal generator includes a fourth p FET having a gate for receiving the set signal. A fifth p FET has a source coupled to the drain of the fourth p FET and has a gate for receiving a VCO clock signal. A fourth n FET has a source coupled to the drain of the fifth n FET and has a gate for receiving the set signal. A sixth p FET has a gate coupled to the drain of the fifth p FET. A fifth n FET has a source coupled to the drain of the sixth p FET and has a gate for receiving the VCO clock signal. A sixth n FET has a source coupled to the drain of the fifth n FET for providing the down signal, and has a gate coupled to the gate of the sixth p FET. A reset circuit, such as a NAND gate, has a first input coupled to the drain of the third p FET, has a second input coupled to the drain of the sixth p FET, and has an output for generating the set signal.

公开(公告)号：US06374361B1

公开(公告)日：2002-04-16

申请号：US09298369

申请日：1999-04-22

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F104

CPC分类号： H03L7/0812 ,  G06F5/06 ,  H03L7/07 ,  H03L7/095 ,  H04L7/0337 ,  H04L25/14

摘要： An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a delay locked loop, for converting the LVDS clock signal into a full-swing clock signal and generating a plurality of clock recovery signals from the converted full-swing clock signal, and a plurality of data recovery signals from the converted full-swing clock signal, and a plurality of data recovery channels, each channel coupled to a data signal and comprising an LVDS converter, a skew adjust circuit, a sampler array, a phase adjusting circuit. The delay locked loop and the data channel circuitry combine to remove skew from LVDS signals by generating multiple clock signals, sampling the data at multiple intervals, using the samples to eliminate skew, and retrieving correct data samples from the data signals. In another embodiment, the sampler array comprises a plurality of transition sampling circuits, for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled data signal responsive to the sampled transition, and a plurality of center sampling circuits, for sampling a center position of each serial bit of data and generating a center sample signal responsive to the sample, and the phase adjusting circuit generating skew control signals responsive to the center sample signals, lock signals, and transition data signals received from the sampler array.

摘要翻译： 公开了一种用于校正数据信号与发送数据和时钟信号并使用低电压差动摆幅的系统中的时钟信号之间的偏差的装置。 该装置在一个实施例中包括延迟锁定环路，用于将LVDS时钟信号转换成全频时钟信号并从转换的全摆频时钟信号产生多个时钟恢复信号，以及多个数据恢复信号 来自转换的全摆频时钟信号和多个数据恢复通道，每个通道耦合到数据信号并且包括LVDS转换器，偏斜调整电路，采样器阵列，相位调整电路。 延迟锁定环路和数据通道电路结合起来，通过产生多个时钟信号，通过使用采样来消除偏差并从数据信号中检索出正确的数据样本，以多个时间间隔对数据进行采样，消除了LVDS信号的偏移。 在另一个实施例中，采样器阵列包括多个转换采样电路，用于在两个相邻串行数据位之间进行采样转换，并产生响应采样转换的锁定信号和采样数据信号，以及多个中心采样电路，用于 采样数据的每个串行位的中心位置，并响应于采样产生一个中心采样信号，相位调整电路根据从采样器阵列接收的中心采样信号，锁定信号和转换数据信号产生偏斜控制信号。

公开(公告)号：US06754478B1

公开(公告)日：2004-06-22

申请号：US09709314

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H04B106

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

摘要： A CMOS low noise amplifier (LNA) is provided that is formed without inductors. The CMOS LNA can be used for a single-chip CMOS RF receiver. The CMOS LNA can include a plurality of amplification stages coupled between an input terminal and an output terminal and a gain controller coupled to each of the plurality of amplifier stages, wherein the CMOS LNA does not include an inductor. Each of the amplification stages can have a symmetrically configured and sized first and second circuits to increase a dynamic range and a feedback loop.

摘要翻译： 提供了一种无电感器形成的CMOS低噪声放大器（LNA）。 CMOS LNA可用于单芯片CMOS射频接收器。 CMOS LNA可以包括耦合在输入端子和输出端子之间的多个放大级和耦合到多个放大器级中的每一个的增益控制器，其中CMOS LNA不包括电感器。 每个放大级可以具有对称配置和尺寸的第一和第二电路以增加动态范围和反馈回路。

公开(公告)号：US06335952B1

公开(公告)日：2002-01-01

申请号：US09121601

申请日：1998-07-24

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03D318

CPC分类号： H03H11/22 ,  H03D7/1441 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/403

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统包括用于接收发射RF信号的天线，用于响应于多相时钟信号产生具有与载波频率不同的频率的多相时钟信号的PLL和具有 载波频率，用于将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合的解调混合单元，以输出具有被载波频率减小的频率的RF信号和A / D转换单元 用于将来自混合单元的RF信号转换成数字信号。

公开(公告)号：US06194947B1

公开(公告)日：2001-02-27

申请号：US09121863

申请日：1998-07-24

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F744

CPC分类号： H04B1/28 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/40 ,  H04B1/403

摘要： A VCO-mixer structure in accordance with the present invention includes a multi-phase VCO and a multi-phase mixer. The VCO includes a plurality of differential delay cells and the mixer includes a differential amplifying circuit and a combining circuit. The differential amplifying circuit of the multi-phase mixer includes two load resistors coupled to two differential amplifiers, respectively. The combining circuit includes bias transistors, first combining unit and second combining unit coupled to the bias transistors, respectively, and a current source coupled to the first and second combining units. The first combining unit includes a plurality of transistor units, and the second combining unit includes a second plurality of transistor units. Preferably, each of the plurality of transistor units includes a plurality of serially connected transistors, wherein the serially connected transistors are coupled in parallel with the serially connected transistors of the plurality of transistor units.

摘要翻译： 根据本发明的VCO混频器结构包括多相VCO和多相混频器。 VCO包括多个差分延迟单元，并且混频器包括差分放大电路和组合电路。 多相混频器的差分放大电路分别包括耦合到两个差分放大器的两个负载电阻。 组合电路分别包括偏置晶体管，第一组合单元和耦合到偏置晶体管的第二组合单元，以及耦合到第一和第二组合单元的电流源。 第一组合单元包括多个晶体管单元，第二组合单元包括第二多个晶体管单元。 优选地，多个晶体管单元中的每一个包括多个串联连接的晶体管，其中串联连接的晶体管与多个晶体管单元的串联连接的晶体管并联耦合。