公开(公告)号：US06831001B2

公开(公告)日：2004-12-14

申请号：US10407642

申请日：2003-04-04

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L214763

CPC分类号： H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.

摘要翻译： 提供了一种用于形成层叠的局部互连的方法，其不在多电平IC器件内延伸到更高级别，以节省IC器件内可用的空间并提高设计灵活性。 在一个实施例中，本发明的方法提供了层叠的局部互连，其将第一组互连的电气特征与一个或多个另外的隔离的互连电特征组或一个或多个隔离的单独电特征电连接。 在第二实施例中，本发明的方法提供了将单个电气特征电连接到一个或多个另外的隔离电气特征的堆叠局部互连。

公开(公告)号：US06806134B2

公开(公告)日：2004-10-19

申请号：US10205131

申请日：2002-07-24

申请人： Jigish D. Trivedi ,  Todd R. Abbott ,  Zhongze Wang

发明人： Jigish D. Trivedi ,  Todd R. Abbott ,  Zhongze Wang

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L21/823864 ,  H01L21/823871

摘要： Devices, structures, and methods for enhancing devices using dual-doped polycrystalline silicon are discussed. One aspect of the present invention includes a p-type strip having a top, a bottom, two sides, and two ends; an n-type strip having a top, a bottom, two sides, and two ends; and a conductive inhibitor strip that adjoins a portion of one of the two sides of the p-type strip and a portion of one of the two sides of the n-type strip so as to inhibit cross-diffusion between the p-type strip and the n-type strip while electrical connection between n-type and p-type polycrystalline silicon is maintained.

摘要翻译： 讨论了使用双掺杂多晶硅增强器件的器件，结构和方法。 本发明的一个方面包括具有顶部，底部，两侧和两端的p型条带; 具有顶部，底部，两侧和两端的n型条带; 以及导电抑制带，其邻接p型条的两侧中的一方的一部分和n型条的两侧的一部分中的一部分，以便抑制p型条和 同时保持n型和p型多晶硅之间的电连接。

公开(公告)号：US06677650B2

公开(公告)日：2004-01-13

申请号：US10047349

申请日：2002-01-14

申请人： Mark Fischer ,  Jigish D. Trivedi ,  Charles H. Dennison ,  Todd R. Abbott ,  Raymond A. Turi

发明人： Mark Fischer ,  Jigish D. Trivedi ,  Charles H. Dennison ,  Todd R. Abbott ,  Raymond A. Turi

IPC分类号： H01L23532

CPC分类号： H01L27/10894 ,  G11C2207/104 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.

摘要翻译： 公开了一种用于制造片上系统的方法，其中包含嵌入式DRAM以及诸如SRAM或逻辑电路的其它组件。 在DRAM和SRAM或逻辑的操作所需的多晶硅插塞之后形成通过硫化物和钨的局部互连。 还公开了由本发明方法制造的片上系统MIM / MIS电容性器件。

公开(公告)号：US06630718B1

公开(公告)日：2003-10-07

申请号：US09360703

申请日：1999-07-26

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L31113

CPC分类号： H01L23/485 ,  H01L21/76895 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a substantially small sheet resistance formed at an exhumed surface of a gate stack, wherein the local interconnect electrically couples a gate electrode of the gate stack with an active region of the semiconductor substrate. The method of forming the local interconnect comprises depositing a gate oxide layer over the substrate, a first polysilicon layer over the gate oxide layer, a laterally conducting layer over the polysilicon layer, a second polysilicon layer over the laterally conducting layer, and an insulating layer over the second polysilicon layer. The intermediate structure is then etched so as to form a plurality of gate stacks. A surface of the second polysilicon layer of a gate stack is exhumed so as to allow subsequent formation of the refractory silicide contact at the exhumed surface. A plurality of spacers are formed along the vertical surfaces of the gate stacks and the substrate is selectively doped so as to form active regions within the substrate. A layer of titanium is deposited over the substrate and a silicon source and/or hardmask material layer is deposited over the titanium layer so as to extend between the gate electrode and the active region of the silicon. The mask layer is then patterned in an etching process so that the mask layer defines the extent of the local interconnect structure. The intermediate structure is then exposed to a high temperature N2/NH3 ambient which induces the formation of refractory silicide contacts at the exhumed surface of the polysilicon layer of the gate stack and at the active region of the substrate as well as the formation of refractory nitride (TiN) at the exposed portions of the titanium layer. A selective wet etch follows which removes the exposed unreacted titanium and exposed titanium nitride and leaves behind the local interconnect.

公开(公告)号：US06613617B2

公开(公告)日：2003-09-02

申请号：US10282420

申请日：2002-10-28

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Todd R. Abbott ,  Chih-Chen Cho

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Todd R. Abbott ,  Chih-Chen Cho

IPC分类号： H01L2184

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.

公开(公告)号：US06541395B1

公开(公告)日：2003-04-01

申请号：US09616959

申请日：2000-07-13

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L2131

CPC分类号： H01L21/823462

摘要： In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

摘要翻译： 根据本发明的一个方面，形成场效应晶体管的半导体处理方法包括在被配置用于形成p型场效应晶体管的第一区域上形成第一栅极电介质层，以及第二区域，用于形成n型场效应 晶体管，半导体衬底上的两个区域。 第一栅极电介质层是在第一栅极介电层内的氮浓度为0.1％摩尔至10.0％摩尔浓度的二氧化硅，与另一个高度位置相比，在一个高度位置处的第一栅极介电层内的氮原子的浓度较高 。 第一栅介质层在第二区域上被移除，同时在第一区域上留下第一栅极介质层，并且在第二区域上形成第二栅极电介质层。 第二栅极电介质层是基本上不含氮原子的二氧化硅材料。 在第一和第二栅极电介质层上形成晶体管栅极，然后在第一区域中的晶体管栅极附近形成p型源极/漏极区域，并且在第二区域中的晶体管栅极附近形成n型源极/漏极区域 。

公开(公告)号：US06498088B1

公开(公告)日：2002-12-24

申请号：US09710399

申请日：2000-11-09

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L214763

CPC分类号： H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention minimizes or eliminates the disadvantages associated with multilevel interconnect structures by providing a method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features. Significantly, in each of its embodiments, the method of the present invention does not require formation of contact plugs and, therefore, obviates the disadvantages associated with contact plug formation. Moreover, portions of the stacked local interconnect structures formed in each embodiment of the method of the present invention not only serve to electrically connect isolated device features but also serve to protect underlying, unrelated IC features from damage during subsequent etch steps. Therefore, the present invention also includes a method for protecting IC features from damage due to inadvertent etching of such features.

摘要翻译： 本发明通过提供一种在多电平IC器件内不扩展到较高级别的层叠局部互连的方法，从而最大限度地减少或消除了与多电平互连结构相关的缺点，从而节省了IC器件内可用的空间并提高了设计灵活性。 在第一实施例中，本发明的方法提供了层叠的局部互连，其将第一组互连的电气特征与一个或多个另外的隔离的互连电特征组或一个或多个隔离的独立电气特征电连接。 在第二实施例中，本发明的方法提供了将单个电气特征电连接到一个或多个另外的隔离电气特征的堆叠局部互连。 重要的是，在其每个实施例中，本发明的方法不需要形成接触塞，因此避免了与接触塞形成相关的缺点。 此外，在本发明的方法的每个实施例中形成的层叠的局部互连结构的部分不仅用于电连接隔离的器件特征，而且还用于保护下一个不相关的IC特征免于在随后的蚀刻步骤期间的损坏。 因此，本发明还包括用于保护IC特征免受由于这种特征的无意蚀刻而损坏的方法。

公开(公告)号：US06323104B1

公开(公告)日：2001-11-27

申请号：US09516639

申请日：2000-03-01

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L2176

CPC分类号： H01L21/76897 ,  H01L21/76232 ,  H01L21/823475 ,  H01L21/823481

摘要： A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials. A first of the materials is received over at least an outermost portion of the sidewall and a second of the materials is received adjacent the first, with the first material being received between the junction isolation region and the second material. A covering insulative material is formed over the trench isolation region and the shallow junction region. A contact opening is etched through the covering insulative material to the shallow junction region and the trench isolation region substantially selective to etch the covering insulative material relative to the first trench isolation material within the trench isolation region. Integrated circuitry independent of the method of fabrication is contemplated.

摘要翻译： 形成集成电路沟槽隔离区域的方法包括将隔离沟槽的第一部分蚀刻成半导体衬底。 第一部分具有横向相对的侧壁和在其间延伸的沟槽基底。 隔离沟槽的第二部分仅通过第一部分沟槽基底的一部分被蚀刻到半导体衬底中。 在第二蚀刻之后，沉积沟槽隔离材料被沉积在隔离沟槽的第一和第二部分内。 在一个实现中，形成集成电路的方法包括在半导体衬底中形成沟槽隔离区域和相邻的浅结区域。 沟槽隔离区域包括邻近浅结区域的侧壁，沟槽隔离区域包括至少两个绝缘沟槽隔离材料。 材料中的第一种被容纳在侧壁的至少最外侧部分上，并且第二材料被接收在第一材料附近，第一材料被接纳在结隔离区域和第二材料之间。 在沟槽隔离区域和浅结区域上形成覆盖绝缘材料。 通过覆盖绝缘材料将接触开口蚀刻到浅结区域和沟槽隔离区域，其基本上选择性地相对于沟槽隔离区域内的第一沟槽隔离材料蚀刻覆盖绝缘材料。 考虑了与制造方法无关的集成电路。

公开(公告)号：US06294464B1

公开(公告)日：2001-09-25

申请号：US09522086

申请日：2000-03-10

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L214763

CPC分类号： H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect

摘要翻译： 用于形成局部互连的工艺包括在半导体层上施加一层金属。 金属硅化物层形成在金属层上。 将金属硅化物层图案化以限定局部互连的边界。 金属硅化物与金属层反应形成复合结构。 复合结构包括金属硅化物，由金属硅化物形成为硅的另一金属硅化物与金属的下层反应，金属硅化物与来自金属和金属的金属的金属间化合物反应。 复合结构残留作为局部互连，去除未反应的金属层

公开(公告)号：US07701059B1

公开(公告)日：2010-04-20

申请号：US08915658

申请日：1997-08-21

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L23/48

CPC分类号： H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.

摘要翻译： 用于形成局部互连的工艺包括在半导体层上施加一层金属。 金属硅化物层形成在金属层上。 将金属硅化物层图案化以限定局部互连的边界。 金属硅化物与金属层反应形成复合结构。 复合结构包括金属硅化物，由金属硅化物形成为硅的另一金属硅化物与金属的下层反应，金属硅化物与来自金属和金属的金属的金属间化合物反应。 复合结构残留作为局部互连，去除未反应的金属层。