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    Mechanisms For Declarative Expression Of Data Types For Data Storage
    1.
    发明申请
    Mechanisms For Declarative Expression Of Data Types For Data Storage 有权
    用于数据存储的数据类型的声明式表达的机制

    公开(公告)号：US20160350091A1

    公开(公告)日：2016-12-01

    申请号：US14722351

    申请日：2015-05-27

    申请人： Prakash Khot ,  Mark Fischer ,  Daniel Philip Arcari

    发明人： Prakash Khot ,  Mark Fischer ,  Daniel Philip Arcari

    IPC分类号： G06F9/45 ,  G06F9/44

    CPC分类号： G06F8/51 ,  G06F3/06 ,  G06F8/315 ,  G06F8/35 ,  G06F8/36 ,  G06F9/44505

    摘要： Computer implemented techniques for storage management include transforming file instances using a modeling language platform that includes a language grammar and a set of language processing rules to transform instances of an entity written in the language grammar into a platform independent code and artifact files and auto-generating by the modeling language platform code to recognize and process input in a given language to deconstruct file instances into pieces that allow further discrete operations to be performed on the file instances.

    摘要翻译： 用于存储管理的计算机实现技术包括使用包括语言语法和一组语言处理规则的建模语言平台来转换文件实例，以将以语言语法编写的实体的实例转换为独立于平台的代码和工件文件和自动生成 通过建模语言平台代码来识别和处理给定语言中的输入，以将文件实例解构为允许对文件实例执行进一步离散操作的部分。

    SEALING ARRANGEMENT FOR SHAFT AND TUNNEL CONSTRUCTIONS
    2.
    发明申请
    SEALING ARRANGEMENT FOR SHAFT AND TUNNEL CONSTRUCTIONS 有权
    密封装置和隧道结构

    公开(公告)号：US20120328369A1

    公开(公告)日：2012-12-27

    申请号：US13516329

    申请日：2010-11-29

    申请人： Heiko Hoeft ,  Holger Gutschmidt ,  Andreas Diener ,  Andreas Artus ,  Mark Fischer ,  Matthias Klug

    发明人： Heiko Hoeft ,  Holger Gutschmidt ,  Andreas Diener ,  Andreas Artus ,  Mark Fischer ,  Matthias Klug

    IPC分类号： E21D11/38 ,  F16J15/06

    CPC分类号： E21D11/385

    摘要： A sealing arrangement for shaft and tunnel constructions. The sealing of gaps between components of shaft and tunnel constructions is improved, in particular if the components are misaligned. For this purpose a) the sealing arrangement (1) comprises at least two components (2), which lie against each other at butt sides (3) so as to form a gap (4), b) the components (2) have an elastic sealing profile (5) on each butt side (3), and c) the sealing profiles (5) of the butt sides (3) that lie against each other lie against each other on a contact plane (6) and bridge the gap (4) in a sealing manner. The sealing profiles (5) have areas (7, 8) of different hardness arranged in alternation in the transverse direction (9) perpendicular to the respective profile longitudinal plane (10), the sealing profiles (5) of butt sides (3) that lie against each other differing from each other in the arrangement of the areas (7, 8) of different hardness in the transverse direction (9).

    摘要翻译： 轴和隧道结构的密封装置。 改进了轴和组件之间的间隙的密封，特别是如果部件不对准。 为此目的a）密封装置（1）包括至少两个部件（2），它们在对接面（3）处彼此相对以形成间隙（4），b）部件（2）具有 每个对接侧（3）上的弹性密封型材（5），以及c）彼此相对的对接面（3）的密封型材（5）在接触平面（6）上彼此抵靠并桥接间隙 （4）。 密封型材（5）具有垂直于相应轮廓纵向平面（10）的横向（9）交替地布置的具有不同硬度的区域（7,8），对接侧面（3）的密封型材（5） 在横向（9）上具有不同硬度的区域（7,8）的布置彼此不同。

    Methods Of Forming Transistors, And Methods Of Forming Memory Arrays
    3.
    发明申请
    Methods Of Forming Transistors, And Methods Of Forming Memory Arrays 有权
    形成晶体管的方法，以及形成记忆阵列的方法

    公开(公告)号：US20120238061A1

    公开(公告)日：2012-09-20

    申请号：US13485892

    申请日：2012-05-31

    申请人： Mark Fischer ,  Sanh D. Tang

    发明人： Mark Fischer ,  Sanh D. Tang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/2454 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

    摘要： Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

    摘要翻译： 一些实施例包括形成垂直晶体管的方法。 结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。 每个鳍片可以具有垂直的晶体管柱，并且每个垂直晶体管柱可以具有底部源极/漏极区域位置，在底部源极/漏极区域位置上方的沟道区域位置，以及顶部源极/漏极区域 渠道区域位置。 导电栅极材料可以沿着鳍片形成，同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。 氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。 在一些实施例中，可以在形成导电栅极材料之后去除氧化物。

    Processes and apparatus having a semiconductor fin
    4.
    发明授权
    Processes and apparatus having a semiconductor fin 有权
    具有半导体散热片的方法和装置

    公开(公告)号：US08154081B2

    公开(公告)日：2012-04-10

    申请号：US13017854

    申请日：2011-01-31

    申请人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

    发明人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

    IPC分类号： H01L27/12

    CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

    摘要： A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.

    摘要翻译： 工艺可以包括首先通过与散热片半导体的侧壁邻接的电介质硬掩模蚀刻沟槽隔离电介质。 可以执行第一蚀刻以暴露侧壁的至少一部分，使得电介质硬掩模在横向方向上比垂直方向更大程度地退回。 该方法可以包括第二蚀刻鳍式半导体以实现减薄的半导体鳍片，其已经在横向后退的硬掩模的阴影之下退化。 减薄的半导体鳍片可以具有可超过光刻极限的特征尺寸。 电子器件可以包括作为场效应晶体管的一部分的变薄的半导体鳍片。

    Methods Of Forming Pluralities Of Vertical Transistors, And Methods Of Forming Memory Arrays
    6.
    发明申请
    Methods Of Forming Pluralities Of Vertical Transistors, And Methods Of Forming Memory Arrays 有权
    形成多个垂直晶体管的方法，以及形成记忆阵列的方法

    公开(公告)号：US20120052640A1

    公开(公告)日：2012-03-01

    申请号：US12872705

    申请日：2010-08-31

    申请人： Mark Fischer ,  Sanh D. Tang

    发明人： Mark Fischer ,  Sanh D. Tang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/2454 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

    摘要： Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

    摘要翻译： 一些实施例包括形成垂直晶体管的方法。 结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。 每个鳍片可以具有垂直的晶体管柱，并且每个垂直晶体管柱可以具有底部源极/漏极区域位置，在底部源极/漏极区域位置上方的沟道区域位置，以及顶部源极/漏极区域 渠道区域位置。 导电栅极材料可以沿着鳍片形成，同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。 氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。 在一些实施例中，可以在形成导电栅极材料之后去除氧化物。

    Semiconductor processing methods
    9.
    发明授权
    Semiconductor processing methods 有权
    半导体加工方法

    公开(公告)号：US07883959B2

    公开(公告)日：2011-02-08

    申请号：US12855585

    申请日：2010-08-12

    申请人： Mark Fischer ,  Terrence B. McDaniel

    发明人： Mark Fischer ,  Terrence B. McDaniel

    IPC分类号： H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L23/5225 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.

    摘要翻译： 本发明包括在与半导体衬底的外围区域或间距区域相关联的线路构造之间形成导电材料的方法。 导电材料可以结合到电接地屏蔽中，和/或可以被配置成产生磁场偏置。 此外，导电材料可以具有用作连接电路元件的电跳线的电隔离段。 本发明还包括在与线圈结构相关联的线路结构之间包括导电材料的半导体结构，其与音调区域和外围区域中的一个或两个相关联。

    EFFICIENT PITCH MULTIPLICATION PROCESS
    10.
    发明申请
    EFFICIENT PITCH MULTIPLICATION PROCESS 有权
    有效的PITCH MULTIPLICATION PROCESS

    公开(公告)号：US20100112489A1

    公开(公告)日：2010-05-06

    申请号：US12687005

    申请日：2010-01-13

    申请人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

    发明人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

    IPC分类号： G03F7/20 ,  H05K3/00

    CPC分类号： H01L29/06 ,  H01L21/0338 ,  H01L21/3088

    摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.

    摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。