公开(公告)号：US07359240B2

公开(公告)日：2008-04-15

申请号：US11322983

申请日：2005-12-29

申请人： Jung-Woo Lee ,  Jae-Yong Jeong

发明人： Jung-Woo Lee ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C2211/5633

摘要： A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

摘要翻译： 一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字， 重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

公开(公告)号：US07245537B2

公开(公告)日：2007-07-17

申请号：US11106640

申请日：2005-04-15

申请人： Jae-Yong Jeong

发明人： Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C16/102

摘要： A nonvolatile memory device and method of programming the device are disclosed. The nonvolatile memory device is adapted to interrupt or resume a programming operation for a memory cell of the device in response to variation in a programming voltage being supplied to the memory cell. The programming operation is typically interrupted or resumed in response to signals generated by a program controller and/or a detector monitoring the programming voltage.

摘要翻译： 公开了一种非易失性存储器件及其编程方法。 非易失性存储器件适于响应于提供给存储器单元的编程电压的变化而中断或恢复器件的存储器单元的编程操作。 响应于由程序控制器和/或监视编程电压的检测器产生的信号，编程操作通常被中断或恢复。

公开(公告)号：US07200049B2

公开(公告)日：2007-04-03

申请号：US11247839

申请日：2005-10-11

申请人： Jae-Woo Park ,  Jae-Yong Jeong

发明人： Jae-Woo Park ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to at least two word lines coupled to ones of the plurality of erased memory cells of the memory cell array. Related devices are also discussed.

摘要翻译： 存储单元阵列中的存储单元将使用擦除操作，随后进行后期程序擦除。 在擦除操作中，擦除电压被施加到存储单元阵列的多个存储单元。 在后期编程操作中，将编程电压同时施加到与存储单元阵列的多个被擦除的存储单元中的一个相连的至少两个字线。 还讨论了相关设备。

公开(公告)号：US20070016722A1

公开(公告)日：2007-01-18

申请号：US11322983

申请日：2005-12-29

申请人： Jung-Woo Lee ,  Jae-Yong Jeong

发明人： Jung-Woo Lee ,  Jae-Yong Jeong

IPC分类号： G06F12/00 ,  G06F13/28 ,  G06F13/00

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C2211/5633

摘要： A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

摘要翻译： 一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字， 重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

公开(公告)号：US07024598B2

公开(公告)日：2006-04-04

申请号：US10003390

申请日：2001-10-30

申请人： Jae-Yong Jeong ,  Sung-Soo Lee

发明人： Jae-Yong Jeong ,  Sung-Soo Lee

IPC分类号： G06F11/00 ,  G11C29/00

CPC分类号： G11C29/44 ,  G11C29/40

摘要： A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.

公开(公告)号：US20130033938A1

公开(公告)日：2013-02-07

申请号：US13483308

申请日：2012-05-30

申请人： Sang-Soo Park ,  Jae-Yong Jeong

发明人： Sang-Soo Park ,  Jae-Yong Jeong

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3454

摘要： A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition.

摘要翻译： 通过执行多个程序循环来编程非易失性存储器件，每个程序循环包括对所选择的字线施加编程电压以改变所选择的存储单元的阈值电压，以及将验证电压施加到所选择的字线以验证 选择的存储单元。 在每个程序循环中，非易失性存储器件确定程序状态，并使程序电压递增根据程序条件确定的量。

公开(公告)号：US08154920B2

公开(公告)日：2012-04-10

申请号：US12712769

申请日：2010-02-25

申请人： In-Mo Kim ,  Jae-Yong Jeong

发明人： In-Mo Kim ,  Jae-Yong Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/34 ,  G11C11/5642 ,  G11C16/32

摘要： A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.

摘要翻译： 一种基于地址的选择位的逻辑电平读取非易失性存储器件中的数据的方法，确定读取与基于地址对应的一个多级存储器单元中存储的数据的第一和第二位的顺序 在选择位的逻辑电平上，根据确定的读数顺序来感测和输出数据的第一和第二位。 在非易失性存储器件中读取数据的方法以及在非易失性存储器件中输入和输出数据的方法可以通过选择读取多重存储器中存储的数据的第一和第二位的顺序来减少初始读取时间 级存储单元，并根据开始地址按顺序读取数据。

公开(公告)号：US07623376B2

公开(公告)日：2009-11-24

申请号：US12035346

申请日：2008-02-21

申请人： Jung-Woo Lee ,  Jae-Yong Jeong

发明人： Jung-Woo Lee ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C2211/5633

摘要： A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

摘要翻译： 一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字， 重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

公开(公告)号：US07447067B2

公开(公告)日：2008-11-04

申请号：US11453991

申请日：2006-06-16

申请人： Jae-Phil Kong ,  Jae-Yong Jeong

发明人： Jae-Phil Kong ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C16/102 ,  G11C11/5628 ,  G11C2211/5621

摘要： A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

摘要翻译： 一种在多级闪速存储器件中对所选单元进行编程的方法包括：确定是否编程所选存储单元的高位或低位，检测存储在所选存储单元中的两位数据的当前逻辑状态， 确定上位或下位的目标逻辑状态，产生用于将上位或下位编程为目标逻辑状态的编程电压和验证电压，以及将编程电压和验证电压施加到连接到所选择的字线的字线 记忆单元

公开(公告)号：US07349263B2

公开(公告)日：2008-03-25

申请号：US11381140

申请日：2006-05-02

申请人： Soo-Han Kim ,  Jae-Yong Jeong

发明人： Soo-Han Kim ,  Jae-Yong Jeong

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/3454 ,  G11C16/3459

摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.

摘要翻译： 非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。 一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。 非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。 控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于 验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有比第一个字线低的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线 步高。