公开(公告)号：US11573740B2

公开(公告)日：2023-02-07

申请号：US17382253

申请日：2021-07-21

Applicant: KIOXIA CORPORATION

Inventor： Marie Sia ,  Yoshihisa Kojima ,  Suguru Nishikawa ,  Riki Suzuki

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

公开(公告)号：US11526301B2

公开(公告)日：2022-12-13

申请号：US16751262

申请日：2020-01-24

Applicant: Kioxia Corporation

Inventor： Takehiko Amaki ,  Yoshihisa Kojima

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10

Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory, and a controller. The controller selects one read method from a plurality of read methods with different time required to perform a read operation on the non-volatile memory and issues a first read command according to the selected one read method to the non-volatile memory.

公开(公告)号：US11442808B2

公开(公告)日：2022-09-13

申请号：US17198451

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Takehiko Amaki ,  Toshikatsu Hida ,  Shunichi Igahara ,  Yoshihisa Kojima ,  Suguru Nishikawa

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0891 ,  G06F12/02 ,  G06F11/07

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

公开(公告)号：US11436136B2

公开(公告)日：2022-09-06

申请号：US16807275

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Takehiko Amaki ,  Toshikatsu Hida ,  Shunichi Igahara ,  Yoshihisa Kojima ,  Suguru Nishikawa

IPC: G06F12/02 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.