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    Memory system
    1.
    发明授权
    Memory system 有权

    公开(公告)号：US11909415B2

    公开(公告)日：2024-02-20

    申请号：US17694057

    申请日：2022-03-14

    Applicant: Kioxia Corporation

    Inventor： Masahiro Kiyooka ,  Riki Suzuki ,  Yoshihisa Kojima

    IPC: H03M13/11 ,  G11C11/4074 ,  G11C11/4096 ,  H03M13/09

    CPC classification number: H03M13/1125 ,  G11C11/4074 ,  G11C11/4096 ,  H03M13/098 ,  H03M13/1108

    Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

    Reading of start-up information from different memory regions of a memory system
    3.
    发明授权
    Reading of start-up information from different memory regions of a memory system 有权

    公开(公告)号：US11042310B2

    公开(公告)日：2021-06-22

    申请号：US16506475

    申请日：2019-07-09

    Applicant: KIOXIA CORPORATION

    Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Takehiko Amaki ,  Shunichi Igahara

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/00 ,  G06F12/02 ,  G06F12/0875 ,  G11C29/52

    Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.

    Memory system and memory system control method
    5.
    发明授权
    Memory system and memory system control method 有权

    公开(公告)号：US11954357B2

    公开(公告)日：2024-04-09

    申请号：US17468895

    申请日：2021-09-08

    Applicant: Kioxia Corporation

    Inventor： Takehiko Amaki ,  Shunichi Igahara ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Riki Suzuki

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

    Memory system chip that suspends transfer phase and resumes transfer phase
    7.
    发明授权
    Memory system chip that suspends transfer phase and resumes transfer phase 有权

    公开(公告)号：US11347398B2

    公开(公告)日：2022-05-31

    申请号：US16913026

    申请日：2020-06-26

    Applicant: Kioxia Corporation

    Inventor： Shizuka Endo ,  Riki Suzuki ,  Yoshihisa Kojima

    IPC: G06F3/06

    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.

    Memory system
    8.
    发明授权
    Memory system 有权

    公开(公告)号：US11086718B2

    公开(公告)日：2021-08-10

    申请号：US16806131

    申请日：2020-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

    IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

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