公开(公告)号：US12046300B2

公开(公告)日：2024-07-23

申请号：US18459501

申请日：2023-09-01

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Kamata ,  Yoshihisa Kojima ,  Suguru Nishikawa

IPC: G11C16/08 ,  G11C7/22 ,  G11C16/32

CPC classification number: G11C16/32 ,  G11C7/22

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

公开(公告)号：US11749350B2

公开(公告)日：2023-09-05

申请号：US18089695

申请日：2022-12-28

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Takehiko Amaki ,  Yoshihisa Kojima ,  Shunichi Igahara

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3459

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US11086718B2

公开(公告)日：2021-08-10

申请号：US16806131

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

公开(公告)号：US12050812B2

公开(公告)日：2024-07-30

申请号：US18318078

申请日：2023-05-16

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Takehiko Amaki

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C11/5642 ,  G11C11/5671

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

公开(公告)号：US11789643B2

公开(公告)日：2023-10-17

申请号：US17685229

申请日：2022-03-02

Applicant: KIOXIA CORPORATION

Inventor： Suguru Nishikawa ,  Toshikatsu Hida ,  Shunichi Igahara ,  Takehiko Amaki

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0679

Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

公开(公告)号：US11734112B2

公开(公告)日：2023-08-22

申请号：US17869881

申请日：2022-07-21

Applicant: Kioxia Corporation

Inventor： Takehiko Amaki ,  Toshikatsu Hida ,  Shunichi Igahara ,  Yoshihisa Kojima ,  Suguru Nishikawa

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0891 ,  G06F12/02 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/073 ,  G06F11/1004 ,  G06F12/0246 ,  G06F12/0891

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

公开(公告)号：US11410729B2

公开(公告)日：2022-08-09

申请号：US17027041

申请日：2020-09-21

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Riki Suzuki ,  Masanobu Shirakawa ,  Toshikatsu Hida

IPC: G06F12/00 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

公开(公告)号：US11244728B2

公开(公告)日：2022-02-08

申请号：US17018147

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Takehiko Amaki ,  Yoshihisa Kojima ,  Shunichi Igahara

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US11869596B2

公开(公告)日：2024-01-09

申请号：US18117520

申请日：2023-03-06

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Riki Suzuki ,  Masanobu Shirakawa ,  Toshikatsu Hida

IPC: G06F12/00 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3459 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C11/5671 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

公开(公告)号：US11693603B2

公开(公告)日：2023-07-04

申请号：US17858294

申请日：2022-07-06

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Takehiko Amaki

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C11/5642 ,  G11C11/5671

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.