公开(公告)号：US09250913B2

公开(公告)日：2016-02-02

申请号：US13524139

申请日：2012-06-15

申请人： Khary J. Alexander ,  Ilia Averbouch ,  Ariel J. Birnbaum ,  Jonathan T. Hsieh ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Ilia Averbouch ,  Ariel J. Birnbaum ,  Jonathan T. Hsieh ,  Chung-Lung K. Shum

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3814

摘要： Embodiments relate to collision-based alternate hashing. An aspect includes receiving an incoming instruction address. Another aspect includes determining whether an entry for the incoming instruction address exists in a history table based on a hash of the incoming instruction address. Another aspect includes based on determining that the entry for the incoming instruction address exists in the history table, determining whether the incoming instruction address matches an address tag in the determined entry. Another aspect includes based on determining that the incoming instruction address does not match the address tag in the determined entry, determining whether a collision exists for the incoming instruction address. Another aspect includes based on determining that the collision exists for the incoming instruction address, activating alternate hashing for the incoming instruction address using an alternate hash buffer.

摘要翻译： 实施例涉及基于冲突的交替散列。 一方面包括接收输入指令地址。 另一方面包括基于输入指令地址的散列来确定历史表中是否存在输入指令地址的条目。 另一方面包括基于确定输入指令地址的条目存在于历史表中，确定输入指令地址是否匹配所确定条目中的地址标签。 另一方面包括基于确定输入指令地址与所确定的条目中的地址标签不匹配，确定对于输入指令地址是否存在冲突。 另一方面包括基于确定对于输入指令地址存在冲突，使用替代散列缓冲器激活输入指令地址的替换散列。

公开(公告)号：US08930627B2

公开(公告)日：2015-01-06

申请号：US13523453

申请日：2012-06-14

申请人： Khary J. Alexander ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Chung-Lung K. Shum

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/08

摘要： A computer program product for mitigating conflicts for shared cache lines between an owning core currently owning a cache line and a requestor core. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes determining whether the owning core is operating in a transactional or non-transactional mode and setting a hardware-based reject threshold at a first or second value with the owning core determined to be operating in the transactional or non-transactional mode, respectively. The method further includes taking first or second actions to encourage cache line sharing between the owning core and the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the first or second value, respectively.

摘要翻译： 一种用于减轻当前拥有高速缓存行和请求者核心的所有核心之间的共享高速缓存行的冲突的计算机程序产品。 计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括确定所拥有的核心是以事务性还是非交易模式操作，并且将所确定的拥有核心分别以事务性或非事务性模式操作的第一或第二值设置为基于硬件的拒绝阈值 。 该方法还包括采取第一或第二动作以响应于请求者核心达到以第一或第二值设置的拒绝阈值的请求的拒绝次数来鼓励拥有核心和请求者核心之间的高速缓存行共享。

公开(公告)号：US08515727B2

公开(公告)日：2013-08-20

申请号：US12051288

申请日：2008-03-19

申请人： Matthew A. Adams ,  Khary J. Alexander ,  Matthew G. Pardini

发明人： Matthew A. Adams ,  Khary J. Alexander ,  Matthew G. Pardini

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F11/261 ,  G06F17/5022 ,  G06F2217/86

摘要： A computer program product stored including machine executable instructions stored on machine readable media, the instructions configured for performing automatic logic build processes and implementing autonomic quality checking, by implementing a method including: providing a model repository for holding at least one component; updating the model repository with at least one component; creating a tag for each sub-component of a selected component of the model repository; associating each tag with a latest version of each respective sub-component; and issuing a component submit notice to identify at least one of a dependency and a priority between selected components. A system is also provided.

摘要翻译： 存储的计算机程序产品包括存储在机器可读介质上的机器可执行指令，所述指令被配置为执行自动逻辑构建过程并执行自主质量检查，所述方法包括：提供用于保持至少一个组件的模型库; 使用至少一个组件更新模型库; 为模型存储库的所选组件的每个子组件创建标签; 将每个标签与每个相应子组件的最新版本相关联; 以及发布组件提交通知以识别所选组件之间的依赖关系和优先级中的至少一个。 还提供了一个系统。

公开(公告)号：US08407453B2

公开(公告)日：2013-03-26

申请号：US13273320

申请日：2011-10-14

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/30

CPC分类号： G06F9/30079 ,  G06F9/30145 ,  G06F9/3867

摘要： Processing within a computing environment is facilitated using an extended DRAIN instruction. An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.

摘要翻译： 使用扩展DRAIN指令便于计算环境内的处理。 扩展DRAIN指令用于在计算环境中停止处理。 该指令包括处理被停止的一个或多个处理阶段的指示。 它还包括一个控制，允许根据需要使处理停滞在额外的周期。

公开(公告)号：US20120036338A1

公开(公告)日：2012-02-09

申请号：US13273320

申请日：2011-10-14

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/30

CPC分类号： G06F9/30079 ,  G06F9/30145 ,  G06F9/3867

摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.

摘要翻译： 扩展DRAIN指令用于在计算环境中停止处理。 该指令包括处理被停止的一个或多个处理阶段的指示。 它还包括一个控制，允许根据需要使处理停滞在额外的周期。

公开(公告)号：US20090240977A1

公开(公告)日：2009-09-24

申请号：US12051367

申请日：2008-03-19

申请人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

发明人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

IPC分类号： G06F11/14

CPC分类号： G06F11/0751 ,  G06F9/30105 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0721

摘要： An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.

摘要翻译： 提供了一种错误检测系统。 该系统包括包括一个或多个数据条目的数据阵列。 复制数据存储选择性地存储数据阵列的第一单个数据条目的副本。 索引生成器选择性地增加引用数据数组的索引。 第一个比较器根据索引将该副本与数据数组中的第二个单个数据条目进行比较。 误差发生器根据第一个比较器的结果产生一个误差信号。

公开(公告)号：US20090240919A1

公开(公告)日：2009-09-24

申请号：US12051527

申请日：2008-03-19

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/312

CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3857

摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

摘要翻译： 一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。 还提供了一种方法和计算机系统。

公开(公告)号：US20090217015A1

公开(公告)日：2009-08-27

申请号：US12035911

申请日：2008-02-22

申请人： Khary J. Alexander ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

发明人： Khary J. Alexander ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3867

摘要： A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.

摘要翻译： 提供了一种用于使用处理器中的推测地址计算来控制重新启动指令取出的系统和方法。 该系统包括预测的目标队列以保持分支预测逻辑（BPL）生成的目标地址值。 系统还包括目标选择逻辑，包括循环队列。 目标选择逻辑从先前推测计算出的来自再循环队列的分支目标值和来自预测目标队列的地址值之间选择保存的分支目标值。 系统还包括比较块，用于响应于所保存的分支目标值与当前计算的分支目标之间的不匹配来识别错误的目标，其中响应于错误的目标重新启动指令获取。

公开(公告)号：US20090210675A1

公开(公告)日：2009-08-20

申请号：US12034042

申请日：2008-02-20

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3826 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

摘要翻译： 提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。 该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。 该系统还包括监视指令流的延迟逻辑。 延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。 响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。