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    Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass
    2.
    发明授权
    Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass 失效
    处理器和方法用于同步加载多个提取序列和流水线阶段结果跟踪，以促进早期地址生成互锁旁路

    公开(公告)号：US07987343B2

    公开(公告)日：2011-07-26

    申请号：US12051527

    申请日：2008-03-19

    申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

    发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/40 ,  G06F9/30

    CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3857

    摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

    摘要翻译： 一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。 还提供了一种方法和计算机系统。

    Method and system for implementing store buffer allocation
    3.
    发明授权
    Method and system for implementing store buffer allocation 有权
    实现存储缓冲区分配的方法和系统

    公开(公告)号：US07870314B2

    公开(公告)日：2011-01-11

    申请号：US12031897

    申请日：2008-02-15

    申请人： Brian D. Barrick ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    发明人： Brian D. Barrick ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    IPC分类号： G06F3/00

    CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3836

    摘要： A method and system for implementing store buffer allocation for variable length store data operations are provided. The method includes receiving a store address request and at least one store data request and stepping through data operations for each of the store data requests and an address range for the store data requests to determine alignment and data steering information used to select a storage buffer destination for the data in the store data requests. The method further includes determining availability of the storage buffer by maintaining a reservation list for each storage buffer, maintaining a count of the number of available entries for each storage buffer, updating the reservation list to reflect a reservation acceptance for designated available entries, and clearing entries upon completion of the processing of store data operations. The method also includes reserving the selected storage buffer when the number of available entries meets or exceeds the number of entries required for the data.

    摘要翻译： 提供了一种用于实现可变长度存储数据操作的存储缓冲区分配的方法和系统。 所述方法包括：接收存储地址请求和至少一个存储数据请求，并且逐步地进行存储数据请求中的每一个的数据操作和存储数据请求的地址范围，以确定用于选择存储缓冲目的地的对准和数据指导信息 用于存储数据请求中的数据。 该方法还包括通过维护每个存储缓冲器的预约列表来确定存储缓冲器的可用性，维护每个存储缓冲器的可用条目数的计数，更新预留列表以反映指定的可用条目的预约接受，以及清除 店铺数据处理完成后的条目。 该方法还包括当可用条目的数量满足或超过数据所需的条目数时，保留所选择的存储缓冲器。

    RECYCLING LONG MULTI-OPERAND INSTRUCTIONS
    4.
    发明申请
    RECYCLING LONG MULTI-OPERAND INSTRUCTIONS 失效
    回收长时间的多操作指令

    公开(公告)号：US20090240914A1

    公开(公告)日：2009-09-24

    申请号：US12051215

    申请日：2008-03-19

    申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30065 ,  G06F9/3832

    摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

    摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

    PROCESSOR AND METHOD FOR SYNCHRONOUS LOAD MULTIPLE FETCHING SEQUENCE AND PIPELINE STAGE RESULT TRACKING TO FACILITATE EARLY ADDRESS GENERATION INTERLOCK BYPASS
    6.
    发明申请
    PROCESSOR AND METHOD FOR SYNCHRONOUS LOAD MULTIPLE FETCHING SEQUENCE AND PIPELINE STAGE RESULT TRACKING TO FACILITATE EARLY ADDRESS GENERATION INTERLOCK BYPASS 失效
    同步负载多处理电路序列和管道阶段结果跟踪的处理器和方法来简化地址生成间接旁路

    公开(公告)号：US20090240919A1

    公开(公告)日：2009-09-24

    申请号：US12051527

    申请日：2008-03-19

    申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

    发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3857

    摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

    摘要翻译： 一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。 还提供了一种方法和计算机系统。

    METHOD, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR ELIMINATING OR REDUCING OPERAND LINE CROSSING PENALTY
    7.
    发明申请
    METHOD, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR ELIMINATING OR REDUCING OPERAND LINE CROSSING PENALTY 有权
    方法，计算机程序产品和用于消除或减少操作线交叉罚款的五金产品

    公开(公告)号：US20090240918A1

    公开(公告)日：2009-09-24

    申请号：US12051296

    申请日：2008-03-19

    申请人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    发明人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3824

    摘要： Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

    摘要翻译： 通过从处理器的数据高速缓存中执行对操作数的初始提取来消除或减少操作数线路交叉处罚。 初始提取是通过允许或允许以参考四字边界未对齐的方式发生初始提取而执行的。 执行用于来自数据高速缓存的相应多个操作数的多个后续提取，其中多个后续提取中的每一个与多个四字边界中的任何一个对齐，以防止多个单独提取请求中的每一个跨越多个 数据缓存中的行。 通过在数据高速缓存的输出处放置操作数缓冲器来存储和合并来自初始提取和多个后续提取的数据并将存储和合并的数据返回到处理器来维持稳定的数据流。

    Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty
    8.
    发明授权
    Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty 有权
    方法，计算机程序产品和硬件产品，用于消除或减少操作线越界处罚

    公开(公告)号：US09201655B2

    公开(公告)日：2015-12-01

    申请号：US12051296

    申请日：2008-03-19

    申请人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    发明人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/38

    CPC分类号： G06F9/3824

    摘要： Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

    摘要翻译： 通过从处理器的数据高速缓存中执行对操作数的初始提取来消除或减少操作数线路交叉处罚。 初始提取是通过允许或允许以参考四字边界未对齐的方式发生初始提取而执行的。 执行用于来自数据高速缓存的相应多个操作数的多个后续提取，其中多个后续提取中的每一个与多个四字边界中的任何一个对齐，以防止多个单独提取请求中的每一个跨越多个 数据缓存中的行。 通过在数据高速缓存的输出处放置操作数缓冲器来存储和合并来自初始提取和多个后续提取的数据并将存储和合并的数据返回到处理器来维持稳定的数据流。

    Processor error checking for instruction data
    9.
    发明授权
    Processor error checking for instruction data 有权
    处理器错误检查指令数据

    公开(公告)号：US08201067B2

    公开(公告)日：2012-06-12

    申请号：US12037038

    申请日：2008-02-25

    申请人： Fadi Y. Busaba ,  Khary J. Alexander ,  Michael Billeci ,  Bruce C. Giamei ,  Vimal M. Kapadia

    发明人： Fadi Y. Busaba ,  Khary J. Alexander ,  Michael Billeci ,  Bruce C. Giamei ,  Vimal M. Kapadia

    IPC分类号： G06F11/00 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

    CPC分类号： G06F11/10

    摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

    摘要翻译： 一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据 数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号 数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。

    Recycling long multi-operand instructions
    10.
    发明授权
    Recycling long multi-operand instructions 失效
    回收长操作数指令

    公开(公告)号：US07962726B2

    公开(公告)日：2011-06-14

    申请号：US12051215

    申请日：2008-03-19

    申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/00 ,  G06F9/44

    CPC分类号： G06F9/30065 ,  G06F9/3832

    摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

    摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。