公开(公告)号：US06662264B2

公开(公告)日：2003-12-09

申请号：US10023701

申请日：2001-12-21

申请人： Kunihiro Katayama ,  Kenichi Kaki ,  Jun Kitahara ,  Tsunehiro Tobita ,  Kazunori Furusawa

发明人： Kunihiro Katayama ,  Kenichi Kaki ,  Jun Kitahara ,  Tsunehiro Tobita ,  Kazunori Furusawa

IPC分类号： G06F1200

CPC分类号： G06F3/0613 ,  G06F3/0601 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/023 ,  G06F12/0246 ,  G06F2003/0694 ,  G06F2212/7208

摘要： A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance. The file memory device includes a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device, and a data access width smaller than the data bus; a file division unit for dividing file data having one or more unit storage data blocks into combined blocks that include a combination of arbitrary unit storage data blocks; a data distribution unit for arbitrarily combining data on the data bus having a unit data size equal to the data access width, and for making the combined data correspond to an arbitrary combination of memory element groups equal in number to the unit size data; and a control unit for controlling the data distribution unit so that each combined block is stored in the file memory device based on a correspondence between the combined block and arbitrary combinations of memory elements.

公开(公告)号：US06272610B1

公开(公告)日：2001-08-07

申请号：US08207749

申请日：1994-03-09

申请人： Kunihiro Katayama ,  Kenichi Kaki ,  Jun Kitahara ,  Tsunehiro Tobita ,  Kazunori Furusawa

发明人： Kunihiro Katayama ,  Kenichi Kaki ,  Jun Kitahara ,  Tsunehiro Tobita ,  Kazunori Furusawa

IPC分类号： G06F1200

CPC分类号： G06F3/0613 ,  G06F3/0601 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/023 ,  G06F12/0246 ,  G06F2003/0694 ,  G06F2212/7208

摘要： A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance. The file memory device includes a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device, and a data access width smaller than the data bus; a file division unit for dividing file data having one or more unit storage data blocks into combined blocks that include a combination of arbitrary unit storage data blocks; a data distribution unit for arbitrarily combining data on the data bus having a unit data size equal to the data access width, and for making the combined data correspond to an arbitrary combination of memory element groups equal in number to the unit size data; and a control unit for controlling the data distribution unit so that each combined block is stored in the file memory device based on a correspondence between the combined block and arbitrary combinations of memory elements.

摘要翻译： 半导体文件存储装置以及包含该装置的信息处理系统使用闪速存储器来实现快速的文件访问性能。 所述文件存储装置包括具有大于所述存储装置的数据总线宽度的单位擦除块大小的存储元件组的并行布置以及小于所述数据总线的数据访问宽度; 文件分割单元，用于将具有一个或多个单元存储数据块的文件数据分成包括任意单位存储数据块的组合的组合块; 数据分配单元，用于任意组合数据总线上具有与数据访问宽度相等的单位数据大小的数据，并且用于使组合数据对应于与单位大小数据相等的存储单元组的任意组合; 以及控制单元，用于基于组合块和存储元件的任意组合之间的对应关系来控制数据分配单元，使得每个组合块被存储在文件存储装置中。

公开(公告)号：US20070088906A1

公开(公告)日：2007-04-19

申请号：US11636629

申请日：2006-12-11

申请人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

发明人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06K7/0021 ,  G06F21/602 ,  G06K7/0047 ,  G06K19/07732

摘要： A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip, wherein, the flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.

摘要翻译： 提供了一种存储装置，其连接用于从主机装置提供的电源和时钟进行操作。 存储器件包括外部端子，存储数据的闪存芯片，处理数据的IC芯片; 以及与外部端子，闪存芯片和IC芯片连接的控制器芯片，其中，闪存芯片，IC芯片和控制器芯片是分立芯片。 控制器芯片根据主机装置的命令将从主机装置输入的数据写入闪存芯片或IC芯片，并将从闪存芯片或IC芯片读取的数据传送到主机装置。

公开(公告)号：US06915427B2

公开(公告)日：2005-07-05

申请号：US09800731

申请日：2001-03-08

申请人： Junichi Maruyama ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Takashi Totsuka ,  Motoyasu Tsunoda ,  Shinya Iguchi ,  Nagamasa Mizushima

发明人： Junichi Maruyama ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Takashi Totsuka ,  Motoyasu Tsunoda ,  Shinya Iguchi ,  Nagamasa Mizushima

IPC分类号： G06F21/00 ,  H04L9/08 ,  H04L9/00 ,  H04L9/32

CPC分类号： G06F21/10

摘要： A license hub including a hub apparatus to which one or more apparatus and devices can be electrically connected, and a safe storage device for storing therein keys used to decode the encrypted contents data is added to the existing system to construct a license network. A controller of the license network acquires the information of various kinds of apparatuses and devices which are electrically connected to the license hub, and determines automatically the apparatus and/or the device suitable for executing the processing when carrying out the playback of contents or movement of the key to execute these processings.

摘要翻译： 一种许可证集线器，包括一个或多个装置和装置可以电连接的集线装置，以及用于存储用于对加密的内容数据进行解码的密钥的安全存储装置被添加到现有系统中以构建许可证网络。 许可证网络的控制器获取与许可证集线器电连接的各种设备和设备的信息，并且在执行内容的播放或移动时自动地确定适合于执行处理的设备和/或设备 执行这些处理的关键。

公开(公告)号：US07350023B2

公开(公告)日：2008-03-25

申请号：US11636629

申请日：2006-12-11

申请人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

发明人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

IPC分类号： G06F12/00

CPC分类号： G06K7/0021 ,  G06F21/602 ,  G06K7/0047 ,  G06K19/07732

摘要： A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip, wherein, the flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.

摘要翻译： 提供了一种存储装置，其连接用于从主机装置提供的电源和时钟进行操作。 存储器件包括外部端子，存储数据的闪存芯片，处理数据的IC芯片; 以及与外部端子，闪存芯片和IC芯片连接的控制器芯片，其中，闪存芯片，IC芯片和控制器芯片是分立芯片。 控制器芯片根据主机装置的命令将从主机装置输入的数据写入闪存芯片或IC芯片，并将从闪存芯片或IC芯片读取的数据传送到主机装置。

公开(公告)号：US07694067B2

公开(公告)日：2010-04-06

申请号：US12015050

申请日：2008-01-16

申请人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

发明人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

IPC分类号： G06F12/00

CPC分类号： G06K7/0021 ,  G06F21/602 ,  G06K7/0047 ,  G06K19/07732

摘要： A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.

摘要翻译： 提供了一种存储装置，其连接用于从主机装置提供的电源和时钟进行操作。 存储器件包括外部端子，存储数据的闪存芯片，处理数据的IC芯片; 以及与外部端子，闪存芯片和IC芯片连接的控制器芯片。 闪存芯片，IC芯片和控制器芯片是分立芯片。 控制器芯片根据主机装置的命令将从主机装置输入的数据写入闪存芯片或IC芯片，并将从闪存芯片或IC芯片读取的数据传送到主机装置。

公开(公告)号：US20090013125A1

公开(公告)日：2009-01-08

申请号：US12015050

申请日：2008-01-16

申请人： Nagamasa MIZUSHIMA ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

发明人： Nagamasa MIZUSHIMA ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

IPC分类号： G06F12/02

CPC分类号： G06K7/0021 ,  G06F21/602 ,  G06K7/0047 ,  G06K19/07732

摘要： A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.

摘要翻译： 提供了一种存储装置，其连接用于从主机装置提供的电源和时钟进行操作。 存储器件包括外部端子，存储数据的闪存芯片，处理数据的IC芯片; 以及与外部端子，闪存芯片和IC芯片连接的控制器芯片。 闪存芯片，IC芯片和控制器芯片是分立芯片。 控制器芯片根据主机装置的命令将从主机装置输入的数据写入闪存芯片或IC芯片，并将从闪存芯片或IC芯片读取的数据传送到主机装置。

公开(公告)号：US07185145B2

公开(公告)日：2007-02-27

申请号：US10476223

申请日：2002-05-29

申请人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

发明人： Nagamasa Mizushima ,  Takashi Tsunehiro ,  Motoyasu Tsunoda ,  Toshio Tanaka ,  Kunihiro Katayama ,  Koichi Kimura ,  Tomihisa Hatano

IPC分类号： G06F12/00

CPC分类号： G06K7/0021 ,  G06F21/602 ,  G06K7/0047 ,  G06K19/07732

摘要： It is an object of the invention to improve security of a storage apparatus. The invention has: a flash memory chip; an IC card chip which can execute a security process (encryption, decryption, etc.); and a controller chip for controlling read/write of data from/into the flash memory chip and the IC card chip in response to a request from a host.

摘要翻译： 本发明的目的是提高存储设备的安全性。 本发明具有：闪存芯片; 可执行安全处理（加密，解密等）的IC卡芯片; 以及用于响应于来自主机的请求，控制从闪存芯片和IC卡芯片的数据的读/写的控制器芯片。

公开(公告)号：US20050235151A1

公开(公告)日：2005-10-20

申请号：US11150326

申请日：2005-06-13

申请人： Junichi Maruyama ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Takashi Totsuka ,  Motoyasu Tsunoda ,  Shinya Iguchi ,  Nagamasa Mizushima

发明人： Junichi Maruyama ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Takashi Totsuka ,  Motoyasu Tsunoda ,  Shinya Iguchi ,  Nagamasa Mizushima

IPC分类号： G06F21/00 ,  H04L9/08 ,  H04L9/00

CPC分类号： G06F21/10

摘要： A licence hub including a hub apparatus to which one or more apparatus and devices can be electrically connected, and a safe storage device for storing therein keys used to decode the encrypted contents data is added to the existing system to construct a licence network. A controller of the licence network acquires the information of various kinds of apparatuses and devices which are electrically connected to the licence hub, and determines automatically the apparatus and/or the device suitable for executing the processing when carrying out the playback of contents or movement of the key to execute these processings.

摘要翻译： 一种许可证集线器，包括一个或多个装置和装置可以电连接的集线装置，以及用于存储用于对加密的内容数据进行解码的密钥的安全存储装置被添加到现有系统中以构建许可证网络。 许可证网络的控制器获取与许可证集线器电连接的各种设备和设备的信息，并且在执行内容的播放或移动时自动地确定适合于执行处理的设备和/或设备 执行这些处理的关键。

公开(公告)号：US08503235B2

公开(公告)日：2013-08-06

申请号：US13298548

申请日：2011-11-17

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C11/34 ,  G11C11/29

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。