公开(公告)号：US11328782B2

公开(公告)日：2022-05-10

申请号：US17247266

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ke Liang ,  Jun Xu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.

公开(公告)号：US20220139465A1

公开(公告)日：2022-05-05

申请号：US17087738

申请日：2020-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/30 ,  G11C16/34 ,  H03K19/17728

Abstract: Memory might include a controller configured to cause the memory to apply a boost voltage level to each capacitance of a plurality of capacitances each connected to a respective node of a sense circuit, selectively discharge each of the nodes through respective memory cells selected for a sense operation, measure a current demand of the plurality of capacitances while each of the nodes is connected to its respective memory cell, determine a deboost voltage level in response to the measured current demand, apply the deboost voltage level to each capacitance of the plurality of capacitances, and determine a respective data state of each memory cell of the plurality of memory cells while the deboost voltage level is applied to each capacitance of the plurality of capacitances.

公开(公告)号：US11211129B2

公开(公告)日：2021-12-28

申请号：US16054206

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Jun Xu

IPC: G11C16/26 ,  G11C11/56

Abstract: Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.

公开(公告)号：US10381085B2

公开(公告)日：2019-08-13

申请号：US15503786

申请日：2016-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu

IPC: G11C16/26 ,  G11C16/16 ,  G11C16/04

Abstract: Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected memory cells, applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells, and applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first and second voltage levels, wherein the magnitude of the third voltage level is greater than the magnitude of both the first voltage level and the second voltage level, and wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the first, second and third voltage levels.