Methods of programming different portions of memory cells of a string of series-connected memory cells

    公开(公告)号:US10861555B2

    公开(公告)日:2020-12-08

    申请号:US16433212

    申请日:2019-06-06

    Inventor: Ke Liang Jun Xu

    Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

    MEMORY ARCHITECTURE FOR ACCESS OF MULTIPLE PORTIONS OF A BLOCK OF MEMORY CELLS

    公开(公告)号:US20210090670A1

    公开(公告)日:2021-03-25

    申请号:US17247266

    申请日:2020-12-07

    Inventor: Ke Liang Jun Xu

    Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.

    METHODS OF PERFORMING READ COUNT LEVELING FOR MULTIPLE PORTIONS OF A BLOCK OF MEMORY CELLS

    公开(公告)号:US20190287619A1

    公开(公告)日:2019-09-19

    申请号:US16433193

    申请日:2019-06-06

    Inventor: Ke Liang Jun Xu

    Abstract: Methods include incrementing a first read count in response to performing a read operation on a memory cell of a block of memory cells, the first read count corresponding to a first portion of memory cells of the block of memory cells; incrementing a second read count in response to performing the read operation on the memory cell of the block of memory cells, the second read count corresponding to a second portion of memory cells of the block of memory cells; resetting the first read count in response to performing an erase operation on the first portion of memory cells of the block of memory cells; and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

    Methods of programming different portions of memory cells of a string of series-connected memory cells

    公开(公告)号:US10418106B2

    公开(公告)日:2019-09-17

    申请号:US15569854

    申请日:2017-08-28

    Inventor: Ke Liang Jun Xu

    Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

    Memory architecture for access of multiple portions of a block of memory cells

    公开(公告)号:US11328782B2

    公开(公告)日:2022-05-10

    申请号:US17247266

    申请日:2020-12-07

    Inventor: Ke Liang Jun Xu

    Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.

    METHODS OF PROGRAMMING DIFFERENT PORTIONS OF MEMORY CELLS OF A STRING OF SERIES-CONNECTED MEMORY CELLS

    公开(公告)号:US20190287620A1

    公开(公告)日:2019-09-19

    申请号:US16433212

    申请日:2019-06-06

    Inventor: Ke Liang Jun Xu

    Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

    MEMORY ARCHITECTURE AND OPERATION
    7.
    发明申请

    公开(公告)号:US20190066787A1

    公开(公告)日:2019-02-28

    申请号:US15569854

    申请日:2017-08-28

    Inventor: Ke Liang Jun Xu

    Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

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